Three-dimensional two-port bit cell

A semiconductor memory, comprising:

• a first layer of a three-dimensional integrated circuit including
• read input/output circuitry,
• a read decoder, and
• a read port array including a plurality of read port cells arranged in rows and columns, each row of read port cells coupled to the read decoder by at least one read word line, and each column of read port cells coupled to the read input/output circuitry by a global bit line;
• and
• a second layer of the three-dimensional integrated circuit disposed vertically above or below the first layer, the second layer including
• write input/output circuitry,
• a write decoder, and
• a bit cell array including a plurality of read port cells arranged in rows and columns, each row of bit cells coupled to the write decoder by a write word line, and each column of bit cells coupled to the write input/output circuitry by a pair of complementary bit lines,
• wherein each bit cell is coupled to a respective read port cell by a via extending from the first layer to the second layer.

A method, comprising:

• forming circuitry on a first layer, the circuitry on the first layer including a read port array comprising a plurality of read port cells;
• forming circuitry on a second layer, the circuitry on the second layer including a bit cell array comprising a plurality of bit cells;
• and
• coupling a read port cell on the first layer to a respective bit cell on the second layer.