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US 2015/0085556 A1Published application
Three dimensional dual-port bit cell and method of using same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei Min CHAN, Wei-Cheng WU, Yen-Huei CHEN
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Abstract
A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.
Claims20
A three dimensional dual-port bit cell comprising:
- a first portion disposed on a first tier, wherein said first portion comprises a plurality of port elements;
- and
- a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein said second portion comprises a latch.
A semi-conductor memory comprising:
- a first tier comprising an access port array portion;
- a second tier vertically stacked with respect to said first tier using at least one via, wherein said second tier comprises a latch array portion;
- and
- at least one three dimensional dual-port bit cell comprising:
- a first portion disposed on said access port array portion, wherein said first portion comprises a plurality of port elements;
- and
- a second portion disposed on said latch array portion, wherein said second portion comprises a latch.
4 more elements
A method, said method comprising:
- disposing a first portion of the three dimensional dual-port bit cell onto a first tier, wherein the first portion includes a plurality of port elements;
- and
- disposing a second portion of the three dimensional dual-port bit cell onto a second tier that is vertically stacked with respect to the first tier, wherein the second portion includes a latch.
Dependencies are inferred from the claim text.