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US 2015/0085546 A1Published application
Multi-level converter apparatus and methods using clamped node bias
AssigneeEaton Corporation
InventorsGeorge William Oughton, JR., Haidong Yu
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Abstract
A multi-level converter includes first and second DC buses, a plurality of transistors coupled in series between the first and second DC buses and a clamp circuit configured to clamp a node joining a first transistor and a second transistor of the plurality of transistors. The converter further includes a bias circuit coupled to the clamped node, which may reduce or prevent voltage stress on the transistors. Related methods of operation are also described.
Claims20
A multi-level converter comprising:
- first and second DC buses;
- a plurality of transistors coupled in series between the first and second DC buses;
- a clamp circuit configured to clamp a node joining a first transistor and a second transistor of the plurality of transistors;
- and
- a bias circuit coupled to the clamped node.
2 more elements
A multi-level converter comprising:
- first and second DC buses;
- an AC node;
- a neutral node;
- first and second transistors coupled in series between the first DC bus and the AC node;
- a diode coupled between the neutral node and a neutral clamped node joining the first and second transistors;
- and
- a resistor coupling the neutral clamped node to the second DC bus.
4 more elements
A method of operating a multi-level converter, the method comprising:
- biasing a clamped node joining a first transistor and a second transistor of the converter to a predetermined voltage to limit a voltage developed across the second transistor.
Dependencies are inferred from the claim text.