Electrostatic Discharge Clamp Circuit For Ultra-Low Power Applications

A clamp circuit for low power applications, comprising:

• a shunting circuit comprised of two shunt transistors electrically coupled between a supply voltage and ground and in series to each other;
• a detection circuit electrically coupled between the supply voltage and ground, wherein the detection circuit is electrically connected via a detection node to the shunting circuit and configured to discharge an electrostatic charge through the two shunt transistors;
• a capacitor electrically coupled between the supply voltage and the detection node;
• and
• a bias circuit electrically coupled to a gate terminal of a first of the two shunt transistors and applies a bias voltage to the gate terminal during absence of an electrostatic discharge event, where the bias circuit is comprised of a first p-type metal-oxide-semiconductor field-effect transistor (MOSFET) coupled in series with a p-type second MOSFET, where a source terminal of the first MOSFET is coupled to the supply voltage, a drain terminal of the first MOSFET is coupled at a bias node to a source terminal of the second MOSFET, a drain terminal of the first MOSFET is coupled to a node interconnecting the two shunt transistors, and the bias node is coupled to the gate terminal of the first of the two shunt transistors.

A clamp circuit for low power applications, comprising:

• a shunting circuit comprised of two shunt transistors electrically coupled between a supply voltage and ground and in series to each other;
• a detection circuit electrically coupled between the supply voltage and ground, wherein the detection circuit is electrically connected via a detection node to the shunting circuit and configured to discharge an electrostatic charge through the two shunt transistors;
• a capacitor electrically coupled between the supply voltage and the detection node;
• and
• a bias circuit electrically coupled to a gate terminal of a first of the two shunt transistors and applies a bias voltage to the gate terminal during absence of an electrostatic discharge event, where the bias circuit is comprised of an even number of diode-connected n-type MOSFETs coupled in series, where one half of the diode-connected MOSFETs are coupled at a bias node to the other half of the diode-connected MOSFETs and the bias node is coupled to the gate terminals of the first MOSFET.