Liquid crystal display and method of charging/discharging pixels of a liquid crystal display

A liquid crystal display (LCD) comprising:

• an LCD panel comprising a plurality of pixels, wherein each pixel of the plurality of pixels is coupled to a corresponding pixel switch;
• a timing controller for enabling data line switches corresponding to 2X switch enable lines;
• a source driving circuit for converting image data into M data voltages for being sent to M first data lines respectively, wherein each of an Mith first data line and an (Mi+1)th first data line of the M first data lines is coupled to X second data lines through X data line switches respectively, pixels corresponding to the Mith first data line are charged or discharged according to an Mith data voltage corresponding to the Mith first data line, pixels corresponding the (Mi+1)th first data line are charged or discharged according to an (Mi+1)th data voltage corresponding to the (Mi+1)th first data line, an Xith data line switch of the X data line switches coupled to the Mith first data line is coupled to an corresponding second data line and an Xith switch enable line of the 2X switch enable lines, and an Xjth data line switch of the X data line switches coupled to the (Mi+1)th first data line is coupled to an corresponding second data line and an (X+Xj)th switch enable line of the 2X switch enable lines;
• and
• a gate driving circuit for enabling N gate lines;
• wherein each pixel of an Nith row of pixels coupled to X second data lines corresponding to the Mith first data line is coupled to an (2Ni−1)th gate line of the N gate lines through a corresponding pixel switch and located at a first side of a corresponding second data line, each pixel of an Nith row of pixel coupled to X second lines corresponding to the (Mi+1)th first data line is coupled to a (2Ni)th gate line of the N gate lines through a corresponding pixel switch and located at the first side of a corresponding second data line, a kth second data line of X second data lines coupled to the (mi+1)th first data line is located between a kth second data line and a (k+1)th second data line of X second data lines coupled to the Mith first data line, enable signals being applied to a gate line and a next gate line corresponding to the gate line are partially overlapping in the N gate lines, and M, N, Mi, Ni, X, Xi, Xj and k are positive integers.