Low power excess loop delay compensation technique for delta-sigma modulators

A delta sigma modulator comprising:

• a first integrator configured to receive an analog input signal and a signal from a first negative feedback coefficient multiplier;
• a second integrator coupled to an output of the first integrator and configured to receive a signal from a second negative feedback coefficient multiplier and a signal from a third negative feedback coefficient multiplier;
• a quantizer coupled to an output of the second integrator and configured to generate a digital output signal;
• a delay element configured to receive the digital output signal and generate a delayed digital output signal;
• a first digital to analog converter (DAC) configured to provide an output signal to the first negative feedback coefficient multiplier and the second negative feedback coefficient multiplier, wherein the first DAC is configured to receive the delayed digital output signal, thereby forming a feedback loop;
• a second DAC configured to provide an output to the third negative feedback coefficient multiplier;
• and
• a differentiator configured to provide an output to the second DAC, wherein the differentiator is configured to receive the delayed digital output signal as a feedback signal.

A method of generating a delayed digital output signal in a delta sigma modulator responsive to an analog input signal, comprising:

• integrating the analog input signal and a first analog signal to generate a first output signal;
• integrating the first analog signal, the first output signal and a second analog signal to generate a second output signal;
• quantizing the second output signal to generate a digital output signal;
• and
• delaying the digital output signal to generate the delayed digital output signal.

A delta sigma modulator comprising:

• an input stage configured to receive an analog input signal and generate a processed error signal;
• an additional summation device configured to receive the processed error signal and an output of a differentiator;
• an output stage configured to receive an output of the additional summation device and generate a delayed digital output signal, wherein the differentiator receives the delayed digital output signal as feedback signal;
• and
• a first digital to analog converter (DAC) configured to receive the delayed digital output signal as feedback signal, wherein the input stage is configured to receive an output of the first DAC.

A method of generating a delayed digital output signal in a delta sigma modulator responsive to an analog input signal, comprising:

• generating a processed error signal from the analog input signal and a first analog signal;
• summing the processed error signal and a second analog signal to generate a second output signal;
• integrating and quantizing the second output signal to generate a digital output signal;
• and
• delaying the digital output signal to generate a delayed digital output signal.