Phase locked loop circuit

A Phase Locked Loop (PLL) circuit, comprising:

• a voltage controlled oscillator (VCO) configured to output an oscillation signal having a frequency corresponding to an inputted voltage;
• a frequency divider configured to divide the oscillation signal and to output a frequency-divided signal;
• a phase comparator configured to compare a phase of the frequency-divided signal and a phase of an input signal from the outside, and to output a first phase comparison signal and a second phase comparison signal which have different polarities;
• a differential amplifier circuit configured to output a control voltage based on a voltage difference between the first phase comparison signal and the second phase comparison signal to the VCO;
• a level shift circuit configured to output a level-shifted signal which is made by shifting a direct current (DC) level of the second phase comparison signal;
• and
• an amplifier circuit configured to output an amplified signal which is an amplified level-shifted signal, wherein
• the differential amplifier circuit generates the control voltage based on the voltage difference between the amplified signal and the first phase comparison signal.