Apparatuses and methods for mitigating uneven circuit degradation of delay circuits
AssigneeMicron Technology, Inc.
InventorScott D. Van De Graaff
Life of this patent
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Abstract
Apparatuses and methods for mitigating uneven circuit degradation of delay circuits are disclosed. In an example method, an imbalance in transistor threshold voltages is detected between a transistor of a first delay circuit and a transistor of a second delay circuit that is series coupled to the first delay circuit, and a clock level of an input clock signal to the first delay circuit is switched responsive to detecting the imbalance.
Claims16
(canceled)
The apparatus of claim 9 wherein the first delay circuit comprises an inverter circuit including a p-channel transistor and an n-channel transistor.
The apparatus of claim 9 wherein the electrical characteristic of the first delay circuit comprises a transistor threshold voltage.
An apparatus, comprising:
- a first delay circuit configured to receive an input clock signal having a first clock level and provide a delay thereto to provide an output signal having a second clock level different than the first clock level;
- a second delay circuit coupled to the first delay circuit and configured to receive the output signal;
- and
- an idle state control circuit configured to determine an imbalance between an electrical characteristic associated with a circuit of the first delay circuit and the electrical characteristic associated with a same circuit of the second delay circuit, the idle state control circuit further configured to cause the clock level of the input clock signal to switch responsive to determining the imbalance.
16-26. (canceled)
Dependencies are inferred from the claim text.