Margin improvement for configurable local clock buffer

A timing margin circuit of a local clock buffer circuit located within a microelectronic device, the timing margin circuit comprising:

• a chain of inverters having an inverter input and an inverter output, the inverter input receiving an input clock signal;
• and
• a NOR logic gate having a first NOR input coupled to the inverter output of the chain of inverters, a second NOR input coupled to an output clock signal that is the inverse of the input clock signal, and a NOR output,
• the NOR gate generating, at the NOR output, a time delayed input clock signal for controlling a falling edge transition of the output clock signal following the output clock signal completing a transition to a logic high.

A method of providing a timing margin for a local clock buffer circuit located within a microelectronic device, the method comprising:

• receiving an input clock signal;
• delaying the received input clock signal along a first delay path having a first chain of inverter logic according to a first operating mode;
• controlling a first falling edge transition of an output clock signal that is derived from the input clock signal based on the delaying of the input clock along the first delay path;
• delaying the received input clock signal along a second delay path having a second chain of inverter logic according to a second operating mode;
• and
• controlling a second falling edge transition of the output clock signal based on the delaying of the input clock along the second delay path,
• the first falling edge transition of the output clock signal corresponding to a pulse mode operation of the local buffer, and the second falling edge transition of the output clock signal corresponding to a master/slave operation of the local buffer.