Command-triggered on-die termination

An integrated circuit device for controlling a dynamic random access memory device (DRAM), the integrated circuit device comprising:

• a first signaling interface to transmit commands to the DRAM;
• and
• control circuitry to transmit to the DRAM via the first signaling interface:
• one or more commands that specify programming of a digital control value within the DRAM, the digital control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response to receiving a write command and during reception of write data corresponding to the write command, and that the DRAM is to decouple from the data interface after reception of the write data corresponding to the write command;
• and
• a write command indicating that write data is to be sampled by the data interface of the DRAM during a first time interval and, as a consequence of transmitting the one or more commands that specify programming of the digital control value, to cause the DRAM to couple the termination impedance to the data interface during the first time interval and decouple the termination impedance from the data interface after the first time interval.

A machine-readable medium that stores data representative of an integrated-circuit memory controller comprising:

• a first signaling interface to transmit commands to a dynamic random access memory device (DRAM);
• and
• control circuitry to transmit to the DRAM via the first signaling interface:
• one or more commands that specify programming of a digital control value within the DRAM, the digital control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response to receiving a write command and during reception of write data corresponding to the write command, and that the DRAM is to decouple from the data interface after reception of the write data corresponding to the write command;
• and
• a write command indicating that write data is to be sampled by a data interface of the DRAM during a first time interval and, as a consequence of transmitting to the DRAM the one or more commands that specify programming of the digital control value, to cause the DRAM to couple the termination impedance to the data interface during the first time interval and decouple the termination impedance from the data interface after the first time interval.