Chip package and method for forming the same

A method for forming a chip package comprising:

• forming a first lower vertical connection, a plurality of second lower vertical connections and a third lower vertical connection in a substrate of a semiconductor device;
• forming a chip select terminal and a plurality of chip select pads on the substrate, wherein the chip select terminal connects to the first lower vertical connection, and the plurality of chip select pads correspondingly connect to the plurality of second lower vertical connections;
• forming an insulation layer on the substrate;
• forming a plurality of upper vertical connections in the insulation layer, wherein the plurality of upper vertical connections correspondingly connect to the plurality of chip select pads and the third lower vertical connection, and in which the third lower vertical connection and the upper vertical connection connecting to the third lower vertical connection form a straight vertical connection;
• and
• forming a plurality of conductors on the insulation layer, wherein the plurality of conductors correspondingly connect to the plurality of upper vertical connections and the straight vertical connection;
• wherein the first lower vertical connection, the plurality of second lower vertical connections and the third lower vertical connection are arranged in two dimensions.