Multi-Chip Package and Method of Formation
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJing-Cheng Lin, Chen-Hua Yu, Jui-Pin Hung, Der-Chyang Yeh
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Abstract
A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least a metal pillar and a plurality of bumps formed on and electrically coupled to the interconnect structures.
Claims20
A device comprising:
- a first semiconductor die embedded in a molding compound layer;
- a surface-mount device embedded in the molding compound layer;
- a plurality of interconnect structures formed on the molding compound layer, wherein:
- the first semiconductor die is electrically coupled to the interconnect structures;
- and
- the surface-mount device is electrically coupled to the interconnect structures through at least a metal pillar;
- and
- a plurality of bumps formed on and electrically coupled to the interconnect structures.
A device comprising:
- a surface-mount device and a first semiconductor die embedded in a molding compound layer, wherein:
- a top surface of a first side of the surface-mount device is exposed outside the molding compound layer;
- and
- a first metal pillar and a second metal pillar are on a second side of the surface-mount device;
- a plurality of interconnect structures over the molding compound layer;
- and
- a plurality of bumps over the interconnect structures.
A device comprising:
- a surface-mount device, a first semiconductor die and a second semiconductor die embedded in a molding compound layer, wherein:
- a top surfaces of a first side of the surface-mount device is exposed outside the molding compound layer;
- and
- the top surface of the first side of the surface-mount device is level with a top surface of a first side of the first semiconductor die;
- and
- a plurality of interconnect structures over the molding compound layer.
Dependencies are inferred from the claim text.