Semiconductor Device Having Plural Memory Chip
AssigneePS4 Luxco S.a.r.l.
InventorAkira Ide
Life of this patent
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Abstract
A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.
Claims1
A semiconductor chip comprising a plurality of circuit blocks, a plurality of buses each transferring data to/from an associated one of the circuit blocks, and a plurality of penetration electrodes each transferring the data to/from an associated one of the buses and arranged penetrating through the semiconductor chip, the penetration electrodes arranged in predetermined stacking positions for aligned coupling in common to other penetration electrodes in one or more stacked semiconductor chips, and each one of the circuit blocks included in the semiconductor chip being enabled in response to an enable signal so that the enabled circuit blocks are arranged in respective different positions as seen in a stacking direction, thereby the data are simultaneously transferred via the penetration electrodes in parallel.
Dependencies are inferred from the claim text.