Semiconductor device
AssigneeRenesas Electronics Corporation
InventorKazuo TOMITA
Life of this patent
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Abstract
The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.
Claims6
(canceled)
A semiconductor device comprising:
- a silicon substrate;
- a first interlayer insulating film having a specific dielectric constant of 3 or less formed over the silicon substrate;
- a second interlayer insulating film having a specific dielectric constant of 3 or less formed on the first interlayer insulating film;
- a passivation film formed over the second interlayer insulating film;
- a seal ring formed within said interlayer insulating film and the second interlayer insulating film so as to surround a circuit formation region of a semiconductor chip;
- and
- a dummy pattern which includes a first dummy metal formed within said first interlayer insulating film, a second dummy metal formed within said second interlayer insulating film, and a plurality of dummy vias formed within the second interlayer insulating film so as to connect the first dummy metal and the second dummy metal in a dicing region of said semiconductor chip, each of the dummy vias connecting the first dummy metal and the second dummy metal,
- the seal ring contacts both the silicon substrate and the passivation film.
Dependencies are inferred from the claim text.