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US 2015/0084135 A1Published application
Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsYoshinao MIURA, Takashi NAKAMURA, Tadatoshi DANNO
Life of this patent
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Abstract
A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.
Claims10
A semiconductor device comprising:
- a substrate;
- and
- a first transistor unit, a second transistor unit, and a third transistor unit which are formed in the substrate and are arranged side by side in this order in a first direction,
- wherein the first transistor unit, the second transistor unit, and the third transistor unit all include a plurality of transistors in which gate electrodes extend in the first direction,
- the semiconductor device further including:
- a first interconnect that extends between the first transistor unit and the second transistor unit in a second direction intersecting the first direction, and is connected to source electrodes of the plurality of transistors of the first transistor unit and source electrodes of the plurality of transistors of the second transistor unit;
- a second interconnect that is located on an opposite side to the first interconnect with the first transistor unit interposed therebetween, extends in the second direction, and is connected to drain electrodes of the plurality of transistors of the first transistor unit;
- a third interconnect that extends between the second transistor unit and the third transistor unit in the second direction, and is connected to drain electrodes of the plurality of transistors of the second transistor unit and drain electrodes of the plurality of transistors of the third transistor unit;
- a fourth interconnect that is located on an opposite side to the third interconnect with the third transistor unit interposed therebetween, extends in the second direction, and is connected to source electrodes of the plurality of transistors of the third transistor unit;
- a first bonding member that is connected to the first interconnect at a plurality of points;
- a second bonding member that is connected to the second interconnect at a plurality of points;
- a third bonding member that is connected to the third interconnect at a plurality of points;
- and
- a fourth bonding member that is connected to the fourth interconnect at a plurality of points.
11 more elements
A semiconductor device comprising:
- a substrate;
- and
- a first transistor unit, a second transistor unit, and a third transistor unit which are formed in the substrate and are arranged side by side in this order in a first direction,
- wherein the first transistor unit, the second transistor unit, and the third transistor unit all include a plurality of transistors in which gate electrodes extend in the first direction,
- the semiconductor device further including:
- a first interconnect that extends between the first transistor unit and the second transistor unit in a second direction intersecting the first direction, and is connected to source electrodes of the plurality of transistors of the first transistor unit and source electrodes of the plurality of transistors of the second transistor unit;
- a second interconnect that is located on an opposite side to the first interconnect with the first transistor unit interposed therebetween, extends in the second direction, and is connected to drain electrodes of the plurality of transistors of the first transistor unit;
- a third interconnect that extends between the second transistor unit and the third transistor unit in the second direction, and is connected to drain electrodes of the plurality of transistors of the second transistor unit and drain electrodes of the plurality of transistors of the third transistor unit;
- a fourth interconnect that is located on an opposite side to the third interconnect with the third transistor unit interposed therebetween, extends in the second direction, and is connected to source electrodes of the plurality of transistors of the third transistor unit;
- a first bonding member that extends in a direction intersecting the first interconnect and the fourth interconnect when seen in a plan view, and is connected to each of the first interconnect and the fourth interconnect;
- and
- a second bonding member that extends in a direction intersecting the second interconnect and the third interconnect when seen in a plan view, and is connected to each of the second interconnect and the third interconnect.
9 more elements
A semiconductor device comprising a first transistor unit, a second transistor unit, and a third transistor unit which are arranged side by side in this order in a first direction,
- wherein the first transistor unit, the second transistor unit, and the third transistor unit all include a plurality of transistors in which gate electrodes extend in the first direction,
- the semiconductor device further including:
- a first interconnect that extends between the first transistor unit and the second transistor unit in a second direction intersecting the first direction, and is connected to source electrodes of the plurality of transistors of the first transistor unit and source electrodes of the plurality of transistors of the second transistor unit;
- a second interconnect that is located on an opposite side to the first interconnect with the first transistor unit interposed therebetween, extends in the second direction, and is connected to drain electrodes of the plurality of transistors of the first transistor unit;
- a third interconnect that extends between the second transistor unit and the third transistor unit in the second direction, and is connected to drain electrodes of the plurality of transistors of the second transistor unit and drain electrodes of the plurality of transistors of the third transistor unit;
- a fourth interconnect that is located on an opposite side to the third interconnect with the third transistor unit interposed therebetween, extends in the second direction, and is connected to source electrodes of the plurality of transistors of the third transistor unit,
- a first upper-layer conductive pattern, provided above the first interconnect, which has a width larger than that of the first interconnect and extends in the second direction;
- a first connecting member that connects the first interconnect to the first upper-layer conductive pattern;
- a second upper-layer conductive pattern, provided above the second interconnect, which has a width larger than that of the second interconnect and extends in the second direction;
- a second connecting member that connects the second interconnect to the second upper-layer conductive pattern;
- a third upper-layer conductor pattern, provided above the third interconnect, which has a width larger than that of the third interconnect and extends the second direction;
- a third connecting member that connects the third interconnect to the third upper-layer conductor pattern;
- a fourth upper-layer conductor pattern, provided above the fourth interconnect, which has a width larger than that of the fourth interconnect and extends in the second direction;
- a first bonding member that is connected to the first upper-layer conductive pattern at a plurality of points;
- a second bonding member that is connected to the second upper-layer conductive pattern at a plurality of points;
- a third bonding member that is connected to the third upper-layer conductor pattern at a plurality of points;
- and
- a fourth bonding member that is connected to the fourth upper-layer conductor pattern at a plurality of points.
15 more elements
A semiconductor device comprising a first transistor unit, a second transistor unit, and a third transistor unit which are arranged side by side in this order in a first direction,
- wherein the first transistor unit, the second transistor unit, and the third transistor unit all include a plurality of transistors in which gate electrodes extend in the first direction,
- the semiconductor device further including:
- a first interconnect that extends between the first transistor unit and the second transistor unit in a second direction intersecting the first direction, and is connected to source electrodes of the plurality of transistors of the first transistor unit and source electrodes of the plurality of transistors of the second transistor unit;
- a second interconnect that is located on an opposite side to the first interconnect with the first transistor unit interposed therebetween, extends in the second direction, and is connected to drain electrodes of the plurality of transistors of the first transistor unit;
- a third interconnect that extends between the second transistor unit and the third transistor unit in the second direction, and is connected to drain electrodes of the plurality of transistors of the second transistor unit and drain electrodes of the plurality of transistors of the third transistor unit;
- a fourth interconnect that is located on an opposite side to the third interconnect with the third transistor unit interposed therebetween, extends in the second direction, and is connected to source electrodes of the plurality of transistors of the third transistor unit;
- a first upper-layer conductive pattern, provided above the first interconnect, which has a width larger than that of the first interconnect and extends in the second direction;
- a first connecting member that connects the first interconnect to the first upper-layer conductive pattern;
- a second upper-layer conductive pattern, provided above the second interconnect, which has a width larger than that of the second interconnect and extends in the second direction;
- a second connecting member that connects the second interconnect to the second upper-layer conductive pattern;
- a third upper-layer conductor pattern, provided above the third interconnect, which has a width larger than that of the third interconnect and extends the second direction;
- a third connecting member that connects the third interconnect to the third upper-layer conductor pattern;
- a fourth upper-layer conductor pattern, provided above the fourth interconnect, which has a width larger than that of the fourth interconnect and extends in the second direction;
- a first bonding member that extends in a direction intersecting the first upper-layer interconnect and the fourth upper-layer interconnect when seen in a plan view, and is connected to each of the first upper-layer interconnect and the fourth upper-layer interconnect;
- and
- a second bonding member that extends in a direction intersecting the second upper-layer interconnect and the third upper-layer interconnect when seen in a plan view, and is connected to each of the second upper-layer interconnect and the third upper-layer interconnect.
13 more elements
Dependencies are inferred from the claim text.