FinFET-Based ESD Devices and Methods for Forming the Same

A device comprising:

• a first fin field effect transistor (finFET) comprising:
• a first plurality of semiconductor fins on a first plurality of semiconductor strips on a substrate,
• a first gate stack over the first plurality of semiconductor fins, and
• a first drain epitaxy semiconductor region on the first plurality of semiconductor strips, the first drain epitaxy semiconductor region having a first thickness proximate the first gate stack and a second thickness distal from the first gate stack, the first thickness being greater than the second thickness;
• and
• a second finFET comprising:
• a second plurality of semiconductor fins on a second plurality of semiconductor strips on the substrate,
• a second gate stack over the second plurality of semiconductor fins, the second gate stack being physically separated and distinct from the first gate stack, wherein the first gate stack is electrically coupled to the second gate stack, and
• a second drain epitaxy semiconductor region on the second plurality of semiconductor strips, the second drain epitaxy semiconductor region having a third thickness proximate the second gate stack and a fourth thickness distal from the second gate stack, the third thickness being greater than the fourth thickness, wherein the first drain epitaxy semiconductor region is electrically coupled to the second drain epitaxy semiconductor region.

A device comprising:

• a plurality of active regions parallel to each other on a substrate;
• a first gate stack and a second gate stack over and crossing the plurality of active regions;
• and
• a drain epitaxy semiconductor region on the plurality of active regions and between the first gate stack and the second gate stack, a first region of the drain epitaxy semiconductor region proximate the first gate stack having a first thickness greater than a second thickness of a second region of the drain epitaxy semiconductor region disposed approximately equidistance between the first gate stack and the second gate stack, a third region of the drain epitaxy semiconductor region proximate the second gate stack having a third thickness greater than the second thickness.