Non-volatile memory devices including blocking insulation patterns with sub-layers having different energy band gaps

A non-volatile memory device comprising:

• a semiconductor substrate;
• a tunnel insulation layer on the semiconductor substrate;
• a charge storage pattern on the tunnel insulation layer;
• a blocking insulation pattern on the charge storage pattern, the blocking insulation pattern comprising,
• a first blocking insulation sub-layer formed of a high-k material,
• a second blocking insulation sub-layer formed of a non-high-k material, and
• a third blocking insulation sub-layer formed of the high-k material,
• wherein the second blocking insulation sub-layer is between the first and third blocking insulation sub-layers;
• and
• a control gate electrode on the blocking insulation pattern.

A non-volatile memory device comprising:

• a semiconductor substrate;
• a tunnel insulation layer on the semiconductor substrate;
• a charge storage pattern on the tunnel insulation layer;
• a blocking insulation pattern on the charge storage pattern, the blocking insulation pattern comprising,
• a first blocking insulation sub-layer comprising Hf, and
• a second blocking insulation sub-layer comprising SiO2;
• and
• a control gate electrode on the blocking insulation pattern, wherein the second blocking insulation sub-layer is between the first blocking insulation sub-layer and the control gate electrode.