Split gate flash cell semiconductor device

A floating gate transistor comprising:

• a floating gate transistor substructure including an oxide disposed over a silicon gate disposed over a gate oxide disposed on a substrate, said oxide having a width less than a width of said silicon gate and said silicon gate including a concave upper surface;
• an inter-gate dielectric disposed over said floating gate transistor substructure;
• and
• a silicon layer with a lower surface disposed over said inter-gate dielectric and said silicon gate, said lower surface facing said silicon gate and including both concave and convex portions overlying an uppermost surface of said floating gate transistor substructure.

A split gate flash cell semiconductor device comprising:

• a duality of floating gate transistors sharing a common source area formed in a substrate, each of said floating gate transistors comprising:
• a floating gate formed on a gate oxide layer, said floating gate terminating laterally at opposed sidewalls;
• a floating gate dielectric disposed on said floating gate and having a bottom forming a conterminous boundary with an upper surface of said floating gate, said floating gate dielectric including a dielectric layer disposed directly on portions of said upper surface;
• and
• a control gate electrode including a lower surface disposed partially over said floating gate dielectric, said lower surface including both concave and convex portions overlying an uppermost surface of said floating gate dielectric.