US 2015/0084110 A1 · FLASH MEMORY AND FABRICATION METHOD THEREOF

Abstract

A method is provided for forming a flash memory. The method includes providing a semiconductor substrate; and forming a first dielectric layer. The method also includes forming a first semiconductor layer on a surface of the first dielectric layer; and performing an ion implantation onto a portion of the first semiconductor layer corresponding to a position of a subsequently formed floating gate. Further, the method includes performing an oxygen ion implantation process onto a portion of the first semiconductor layer between the position of the subsequently formed floating gate and the position of a subsequently formed first select gate to form an oxide layer; and forming a second dielectric layer having an opening exposing the position of the first select gate. Further, the method also includes forming a second semiconductor layer on the second dielectric layer; and forming a flash cell and a select gate structure.

Claims20

Dependent claims

A method for fabricating a flash memory, comprising:

providing a semiconductor substrate
forming a first dielectric layer on a surface of the semiconductor substrate;
forming a first semiconductor layer on a surface of the first dielectric layer;
performing an ion implantation process onto a portion of the first semiconductor layer corresponding to a position of a subsequently formed floating gate;
performing an oxygen ion implantation process onto a portion of the first semiconductor layer between the position of the subsequently formed floating gate and the position of a subsequently formed first select gate to form an oxide layer;
forming a second dielectric layer having an opening exposing the position of the first select gate on the first semiconductor layer;
forming a second semiconductor layer on the second dielectric layer;
and
forming a flash cell and a select gate structure by etching the first dielectric layer, the first semiconductor layer, the oxide layer, the second dielectric layer and the second semiconductor layer.

6 more elements

A flash memory, comprising:

a semiconductor substrate;
a flash cell having a floating gate dielectric layer formed on a surface of the semiconductor substrate, a floating gate formed on the floating gate dielectric layer, a control gate dielectric layer formed on the floating gate and the a control gate formed on the control gate dielectric layer formed on the semiconductor substrate;
a select gate structure having a select gate dielectric layer formed on the surface of the semiconductor substrate, a first select gate formed on the select gate dielectric layer and a second select gate formed on the first select gate formed on the semiconductor substrate;
a co-source/drain region formed in the semiconductor substrate between the flash cell and the select gate structure;
a source region in the semiconductor substrate at the other side of the flash cell;
and
a drain region in the semiconductor substrate at the other side of the select gate structure.

4 more elements

Dependencies are inferred from the claim text.

Flash memory and fabrication method thereof

Life of this patent

Flash memory and fabrication method thereof

Life of this patent

Abstract

Claims20