Semiconductor devices and methods of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHauk Han, Yong-IL Kwon, JungSuk Oh, Tae sun Ryu, Jeonggil Lee
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Abstract
A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.
Claims21
1-20. (canceled)
A semiconductor device, comprising:
- a lower insulating pattern disposed on a substrate;
- a lower gate pattern disposed on the lower insulating pattern;
- a residual insulating pattern disposed on the lower gate pattern;
- a first upper gate pattern disposed on the residual insulating pattern, wherein an opening is formed in the first upper gate pattern, the residual insulating pattern and a portion of the lower gate pattern;
- a diffusion barrier pattern disposed on an upper surface of the first upper gate pattern and a side surface of the first upper gate pattern, wherein the side surface of the first upper gate pattern is adjacent to the opening;
- and
- a second upper gate pattern disposed on the diffusion harrier pattern and filling the opening.
A NAND flash memory device comprising:
- a string selection gate;
- a ground selection gate;
- and
- a plurality of cell gates, the plurality of cell gates electrically connected between the string selection gate and the ground selection gate, wherein at least one of the string selection gate and the ground selection gate comprises:
- a lower insulating pattern disposed on a substrate;
- a lower gate pattern disposed on the lower insulating pattern;
- a residual insulating pattern disposed on the lower gate pattern;
- a first upper gate pattern disposed on the residual insulating pattern, wherein an opening is formed in the first upper gate pattern, the residual insulating pattern and a portion of the lower gate pattern;
- a diffusion barrier pattern disposed on an upper surface of the first upper gate pattern and a side surface of the first upper gate pattern, wherein the side surface of the first upper gate pattern is adjacent to the opening;
- and
- a second upper gate pattern disposed on the diffusion barrier pattern and filling the opening.
A semiconductor device, comprising;
- a cell gate electrode and a selection gate electrode, wherein the selection gate electrode includes:
- a lower insulating pattern disposed on a substrate;
- a lower gate pattern disposed on the lower insulating pattern;
- a residual insulating pattern disposed on the lower gate pattern;
- a first upper gate pattern disposed on the residual insulating pattern, wherein an opening is formed in the first upper gate pattern, the residual insulating pattern and a portion of the lower gate pattern;
- a diffusion harrier pattern disposed on an upper surface the first upper gate pattern and a side surface of the first upper gate pattern, wherein the diffusion barrier pattern disposed on the side surface of the first upper gate pattern forms a portion of a sidewall of the opening;
- and
- a second upper gate pattern disposed on the diffusion barrier pattern and filling the opening.
Dependencies are inferred from the claim text.