Thin film transistor substrate and display
AssigneeInnolux Corporation
InventorKuan-Feng LEE
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Abstract
An embodiment of the invention provides a thin film transistor substrate includes: a substrate; and a plurality of transistors, wherein each of the transistors includes a gate electrode disposed on the substrate; a first diffusion barrier layer disposed on the substrate and covering an upper surface and a ring sidewall of the gate electrode; a gate insulating layer disposed on the first diffusion barrier layer; an active layer disposed on the gate insulating layer and over the gate electrode; a source electrode disposed on the substrate and electrically connected to the active layer; a drain electrode disposed on the substrate and electrically connected to the active layer; and a protective layer covering the source electrode and the drain electrode.
Claims14
A thin film transistor substrate, comprising:
- a substrate;
- and
- a plurality of thin film transistors disposed over the substrate, wherein each of the thin film transistors comprises:
- a gate electrode disposed on the substrate;
- a first diffusion barrier layer disposed on the substrate and covering the gate electrode;
- a gate insulating layer disposed on the first diffusion barrier layer;
- a metal oxide disposed on the gate insulating layer and over the gate electrode;
- a source electrode disposed on the substrate and electrically connected to the metal oxide;
- a drain electrode disposed on the substrate and electrically connected to the metal oxide,
- an insulating layer disposed on the metal oxide and covering the gate insulating layer, wherein the source electrode and the drain electrode are disposed over and passes through the insulating layer to connect to the metal oxide;
- and
- a protective layer covering the source electrode and the drain electrode.
A thin film transistor substrate, comprising:
- a substrate;
- and
- a plurality of thin film transistors disposed over the substrate, wherein each of the thin film transistors comprises:
- a gate electrode disposed on the substrate;
- a first diffusion barrier layer disposed on the substrate and covering the gate electrode;
- a gate insulating layer disposed on the first diffusion barrier layer, wherein the gate electrode has an upper surface and a sidewall;
- a third diffusion barrier layer disposed between the gate electrode and the first diffusion barrier layer, wherein the third diffusion barrier layer is disposed on the upper surface of the gate electrode and a projection of the third diffusion barrier is surround by the sidewall;
- a metal oxide disposed over the gate insulating layer and over the gate electrode;
- a source electrode disposed over the substrate and electrically connected to the metal oxide;
- a drain electrode disposed over the substrate and electrically connected to the metal oxide;
- and
- a protective layer covering the source electrode and the drain electrode.
Dependencies are inferred from the claim text.