Method for manufacture of fine line circuitry
AssigneeAtotech Deutschland GmbH
InventorsRichard Nichols, Don Jang, Harald Riebel, Frank Brüning
Life of this patent
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Abstract
The present invention relates to a method for manufacture of fine line circuitry in the manufacture of printed circuit boards, IC substrates and the like. The method utilizes a first conductive layer on the smooth surface of a build-up layer and a second conductive layer selected from electrically conductive polymers, colloidal noble metals and electrically conductive carbon particles on the roughened walls of at least one opening which are formed after depositing the first conductive layer.
Claims21
1-14. (canceled)
A method for manufacture of fine line circuitry comprising, in this order, the steps of
- (i) providing a dielectric build-up layer having a front side and a back side surface area and wherein at least a portion of the back side surface area comprises a copper area and wherein a dielectric layer is attached to said back side surface area and wherein an adhesion promoting layer selected from the group consisting of organosilane compounds and nanometer-sized oxide particles having at least one attachment group bearing a functional chemical group suitable for binding to the substrate is attached to the front side surface area of the build-up layer, wherein the adhesion promoting layer selected from organosilane compounds is formed by
- (a) treating said surface with a solution comprising at least one organosilane compound and
- (b) treating said surface with a solution comprising an oxidizing agent,
- (ii) depositing a first conductive layer onto the adhesion promoting layer,
- (iii) forming at least one opening which extends through the first conductive layer, the adhesion promoting layer and the build-up layer to the at least one copper area,
- (iv) cleaning the dielectric side walls and the copper area of the at least one opening to obtain cleaned side walls and a cleaned copper area,
- (v) forming a second conductive layer on at least the cleaned side walls wherein the second conductive layer is selected from the group consisting of electrically conductive polymers, colloidal particles comprising a noble metal, electrically conductive carbon particles and copper deposited by electroless plating,
- (vi) applying a resist layer onto the first conductive layer or onto the second conductive layer in case the second conductive layer is copper deposited by electroless plating;
- and patterning said resist layer,
- (vii) depositing a copper layer by electroplating into the openings of the patterned resist layer,
- (viii) removing the patterned resist layer and
- (ix) removing those portions of the first conductive layer or the second conductive layer in case the second conductive layer is copper deposited by electroless plating, which are not covered by the electroplated copper layer.
Dependencies are inferred from the claim text.