Nanowires and nanowire fielde-effect transistors

A nanowire field-effect transistor, comprising:

• a first semiconductor substrate;
• a buried layer on the first semiconductor substrate;
• a nanowire suspended over the buried layer by a through-hole separating the nanowire from a top surface of the buried layer, wherein the nanowire comprises:
• a first nanowire deposited on the buried layer, the first nanowire comprising a first polygon-shaped cross-section having a first number of sides, and
• a semiconductor layer deposited on all exposed surface of the first nanowire, wherein the semiconductor layer has a second polygon-shaped cross-section containing the first polygon-shaped cross-section of the first nanowire, the second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number of sides,
• wherein the nanowire is an annealed nanowire from annealing of the semiconductor layer and the first nanowire, to remove a substantial number of vertexes of the second polygon-shaped cross-section of the semiconductor layer, wherein the nanowire has a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section;
• a gate structure covering the nanowire;
• and
• a source and a drain connecting with the nanowire and both disposed on the buried layer.

A nanowire field-effect transistor, comprising:

• a first semiconductor substrate;
• a buried layer on the first semiconductor substrate;
• a second semiconductor substrate on the buried layer, the second semiconductor substrate comprising a nanowire, a source, and a drain, the nanowire having one end connecting to the source and the other end connecting to the drain on the buried layer,
• wherein the nanowire comprises:
• a first nanowire deposited over the buried layer, the first nanowire comprising a first polygon-shaped cross-section having a first number of sides, and
• a semiconductor layer deposited on all exposed surface of the first nanowire, wherein the semiconductor layer has a second polygon-shaped cross-section containing the first polygon-shaped cross-section of the first nanowire, the second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number of sides,
• wherein the nanowire is an annealed nanowire from annealing of the semiconductor layer and the first nanowire, to remove a substantial number of vertexes of the second polygon-shaped cross-section of the semiconductor layer, wherein the nanowire has a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section;
• and
• a gate structure covering the nanowire.