Single Spacer Process for Multiplying Pitch by a Factor Greater Than Two and Related Intermediate IC Structures
AssigneeMicron Technology, Inc.
InventorsDavid H. Wells, Mirzafer K. Abatchev
Life of this patent
Estimating the term…
Abstract
Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
Claims21
(canceled)
An integrated circuit, comprising:
- a first plurality of sets of interconnects, each set comprising 2n interconnects, wherein n is a whole number and is 2 or greater;
- and
- a second plurality of sets of interconnects, each set comprising 2n interconnects,
- wherein the sets of interconnects of the first and second plurality are interdigitated.
An integrated circuit, comprising:
- two pluralities of interdigitated groups of conductive lines,
- wherein each group of conductive lines comprises 2n lines, wherein n is a whole number and is 2 or greater.
A computer system, comprising:
- an integrated circuit, comprising:
- a first plurality of sets of interconnects, each set comprising 2n interconnects, wherein n is a whole number and is 2 or greater;
- and
- a second plurality of sets of interconnects, each set comprising 2n interconnects,
- wherein the sets of interconnects of the first and second plurality are interdigitated.
Dependencies are inferred from the claim text.