# US 2015/0040136 A1 · System constraints-aware scheduler for heterogeneous computing architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0040136 A1 - Document ID: US20150040136A1 - Status: Published application - Kind: A1 - Application number: 14/106,022 - Filed: 2013-12-13 - Published: 2015-02-05 - Earliest claimed: 2013-08-01 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments, Incorporated - Inventors: Katrin Matthes; Damien Ramonda - Web page: https://patentgrep.com/patent/US20150040136A1 ## CPC - G06F 9/5094: {where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Processors, systems, and methods are arranged to schedule tasks on heterogeneous processor cores. For example, a scheduler is arranged to perform a heuristics based function for allocating operating system tasks to the processor cores. The system includes a hint generator providing a system constraints-aware function that biases the scheduler to select a processor core depending on the change in one or more performance constraint parameters. ## Claims ### Claim 1 A processor, comprising: a plurality of processor cores, each of which is arranged to perform processing tasks, and wherein at least one of the processor cores is of a different architecture than the other core(s); a scheduler that is arranged to receive task identifiers of respective processing tasks from a task queue and to allocate a selected core of the processor cores for each respective processing task received from the task queue; and a hint generator that is arranged to monitor one or more performance constraint parameters of the processor during operation of the processor and to generate a hint in response to the monitored one or more performance parameters, wherein the scheduler is arranged to allocate the respective processing task from the task queue to the selected core in response to the generated hint. ### Claim 2 (depends on 1) The processor of claim 1, wherein the hint generator is arranged to compare a first monitored performance constraint parameter with a first related system constraint setting to determine a bias threshold, wherein the scheduler is arranged to allocate the respective processing task from the task queue to the selected core in response to the determined bias threshold. ### Claim 3 (depends on 2) The processor of claim 2, wherein the hint generator is arranged to select a first and a second related system constraint setting in response to the respective task identifier, wherein the second system constraint setting is a performance constraint parameter of a different type than the first respective system constraint. ### Claim 4 (depends on 3) The processor of claim 3, wherein the first respective system constraint setting is a performance constraint parameter of a type that includes temperature constraints. ### Claim 5 (depends on 4) The processor of claim 4, wherein the second respective system constraint setting is a performance constraint parameter of a type includes either user mode constraints or power constraints. ### Claim 6 (depends on 2) The processor of claim 2, wherein the hint generator is arranged to store a first system constraint setting having a first constraint type, wherein a first threshold is determined by comparing the first stored physical constraint with a related performance constraint parameter of the first type. ### Claim 7 (depends on 6) The processor of claim 6, wherein the first threshold reflects a bias towards selecting a first or a second core type wherein the first core type consumes more power than the second core type. ### Claim 8 (depends on 7) The processor of claim 7, wherein the hint generator is arranged to store a second system constraint setting having a second constraint type, wherein a second threshold is determined by comparing the second stored physical constraint with a related performance constraint parameter, wherein the second constraint type is different from the first constraint type, and wherein the second threshold reflects a bias towards selecting the first or the second core type. ### Claim 9 (depends on 8) The processor of claim 8, wherein the bias threshold is determined in response to the first and second thresholds. ### Claim 10 (depends on 8) The processor of claim 8, wherein the bias threshold is determined in response determining the greater of the first and second thresholds. ### Claim 11 (depends on 10) The processor of claim 10, wherein the bias threshold reflects a bias towards a core type that is associated with the lesser of the first and second thresholds. ### Claim 12 (depends on 11) The processor of claim 11, comprising a heterogeneous multicore scheduler that is arranged to receive the bias threshold and to allocate the selected core of the processor cores in accordance with the bias reflected towards the core type that is associated with the greater of the first and second thresholds. ### Claim 13 (depends on 1) The processor of claim 1, wherein the one or more performance constraint parameters include a user defined mode, wherein each user mode is associated with a threshold value. ### Claim 14 (depends on 1) The processor of claim 1, wherein a first monitored performance constraint parameter is measured in response to semiconductor junction temperature of the processor during operation of the task queue. ### Claim 15 A scheduling system, comprising: a scheduler that is communicatively coupled with a plurality of heterogeneous processor cores and with a task queue including one or more processing tasks, and wherein the scheduler is arranged to allocate the processing task from the task queue to a selected processor core of the plurality of processor cores based on a heuristic function and a load balancing mechanism; and a hint generator that is arranged to monitor one or more predetermined performance constraint parameters of the processor during operation of the scheduler and to generate a hint for biasing a selection of a core type of the plurality of heterogeneous processor cores in response to the monitored one or more performance parameters, wherein the generated hint is arranged to bias a selection of a core type of the plurality of heterogeneous processor cores, and wherein the scheduler is arranged to allocate the selected core of the processor cores in accordance with the generated hint. ### Claim 16 (depends on 15) The system of claim 15, wherein the hint is a bias threshold generated in response to comparing each monitored performance constraint parameters with one or more related system constraints each of which is associated with a respective core type. ### Claim 17 (depends on 16) The system of claim 16, wherein the scheduler allocates processing tasks in accordance with the bias threshold when the bias threshold exceeds a predefined threshold value, and wherein each monitored performance constraint parameter includes a temperature, a user defined mode, or a battery level of a computing device. ### Claim 18 A method, comprising: receiving from a task queue a succession of processing tasks for execution upon a plurality of heterogeneous processor cores in a processor, each of which is arranged to perform the respective processing tasks, wherein at least one of the processor cores is heterogeneous with respect to the architecture of at least one other of the processor cores, and wherein each processing task is associated with a respective task identifier; monitoring one or more performance constraint parameters of the processor during operation of the processor; generating a hint in response to comparing a first monitored performance constraint parameter with a first related system constraint setting, wherein the generated hint is arranged to bias a selection of a core type of the plurality of heterogeneous processor cores; and allocating each respective processing tasks to a selected processing core that is selected in response to a core type. ### Claim 19 (depends on 18) The method of claim 18, further comprising selecting the first related system constraint setting in response to the respective task identifier. ### Claim 20 (depends on 19) The method of claim 19, further comprising selecting a second related system constraint setting in response to the respective task identifier, wherein the second system constraint setting is a performance constraint parameter of a different type than the first respective system constraint.