Sequential delay analysis by placement engines

A method for designing an integrated circuit (IC), the method comprising:

• receiving a specification of a particular path between a source node and a target node in the IC, the particular path comprises a set of computational elements and a set of clocked elements;
• attributing a positive combinational delay to each of the computational elements and a negative combinational delay to each of the clocked elements, wherein the negative combinational delay attributed to each clocked element is based on a clock period for operating the clocked element;
• computing a sequential delay for the particular path by adding the combinational delays attributed to the clocked elements and the computational elements;
• and
• determining whether the sequential delay of the particular path meets a timing requirement.

A method for designing an integrated circuit (IC), the method comprising:

• receiving a specification of a particular path between a source node and a target node in the IC, the particular path comprises a set of computational elements and a set of clocked elements, wherein each computational elements is attributed a positive timing delay and each clocked element is attributed a negative delay that is based on a clock period for operating the clocked element;
• computing a cumulative timing delay from the source node to the target node by adding the timing delays attributed to the set of computational elements and the set of clocked elements;
• and
• determining whether the particular path meets a timing requirement at the target node based on the computed cumulative timing delay.

A non-transitory computer readable medium storing a program for execution by one or more processing units, the program comprising sets of instructions for:

• receiving a specification of a particular path between a source node and a target node in the IC, the particular path comprises a set of computational elements and a set of clocked elements;
• attributing a positive combinational delay to each of the computational elements and a negative combinational delay to each of the clocked elements, wherein the negative combinational delay attributed to each clocked element is based on a clock period for operating the clocked element;
• computing a sequential delay for the particular path by adding the combinational delays attributed to the clocked elements and the computational elements;
• and
• determining whether the sequential delay of the particular path meets a timing requirement.