Stress Migration Mitigation

A computer program product for configuring a semiconductor device, the computer program product comprising one or more computer-readable storage media having stored thereon computer-executable instructions that, when executed by one or more processors of a computing system, cause the computing system to perform a method, the method comprising:

• identifying an interconnect having a width less than three times a minimum line dimension of the semiconductor device and having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device;
• placing a conductive structure adjacent the interconnect to define a pair of segments of the interconnect;
• wherein each segment has a length no greater than the stress-induced void formation characteristic length of the interconnect;
• and
• wherein the conductive structure is selected from the group consisting of a decoy via connected to the interconnect, a floating tile disposed along the interconnect, a tab that laterally extends outward from the interconnect, and a jumper from a first metal layer in which the interconnect is disposed to a second metal layer.

A computer-implemented method of configuring a semiconductor device, the method comprising:

• identifying an interconnect having a width less than three times a minimum line dimension of the semiconductor device and having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device;
• determining, with a processor, whether a first via space is available to add a redundant via to the interconnect at a position along the interconnect to define a pair of segments of the interconnect having respective lengths no greater than the stress-induced void formation characteristic length;
• and
• if the first via space is not available, determining, with the processor, whether a second space is available to add an extraneous conductive structure adjacent the interconnect at the position along the interconnect to define the pair of segments of the interconnect having respective lengths no greater than the stress-induced void formation characteristic length.