US 2015/0040090 A1 · DISCRETIZING GATE SIZES DURING NUMERICAL SYNTHESIS

Abstract

Systems and techniques are described for discretizing gate sizes during numerical synthesis. Some embodiments can receive an optimal input capacitance value for an input of an optimizable cell, wherein the input capacitance value is determined by a numerical solver that is optimizing the circuit design. Note that the circuit design may be optimized for different objective functions, e.g., best delay, minimal area under delay constraints, etc. Next, the embodiments can identify an initial library cell in a technology library whose input capacitance value is closest to the optimal input capacitance value. The embodiments can then use the initial library cell to attempt to identify a better (in terms of the objective function that is being optimized) library cell in the technology library. The delay computations used during this process are also minimized.

Claims16

Dependent claims

A method for discretizing cell sizes during numerical synthesis, the method comprising:

receiving an optimal input capacitance value for an input of an optimizable cell, wherein the input of the optimizable cell is driven by an output of a driver cell, and wherein the input capacitance value is determined by a numerical solver that is optimizing a circuit design for best delay;
identifying a first library cell whose input capacitance value is closest to the optimal input capacitance value, wherein the first library cell is selected from a technology library;
computing a delay from an input of the driver cell to an output of the optimizable cell assuming the first library cell is instantiated at the optimizable cell;
and
identifying a second library cell from the technology library, wherein the input capacitance value of the second library cell is less than or equal to the input capacitance value of the first library cell, and wherein instantiating the second library cell at the optimizable cell would improve the delay from the input of the driver cell to the output of the optimizable cell.

2 more elements

An apparatus, comprising:

a processor;
and
a non-transitory computer-readable storage medium storing instructions that, when executed by the processor, cause the apparatus to perform a method for discretizing cell sizes during numerical synthesis, the method comprising:
receiving an optimal input capacitance value for an input of an optimizable cell, wherein the input of the optimizable cell is driven by an output of a driver cell, and wherein the input capacitance value is determined by a numerical solver that is optimizing a circuit design for best delay;
identifying a first library cell whose input capacitance value is closest to the optimal input capacitance value, wherein the first library cell is selected from a technology library;
computing a delay from an input of the driver cell to an output of the optimizable cell assuming the first library cell is instantiated at the optimizable cell;
and
identifying a second library cell from the technology library, wherein the input capacitance value of the second library cell is less than or equal to the input capacitance value of the first library cell, and wherein instantiating the second library cell at the optimizable cell would improve the delay from the input of the driver cell to the output of the optimizable cell.

5 more elements

A method for discretizing cell sizes during numerical synthesis, the method comprising:

receiving an optimal input capacitance value for an input of an optimizable cell, wherein the input of the optimizable cell is driven by an output of a driver cell, and wherein the input capacitance value is determined by a numerical solver that is optimizing a circuit design for minimal area under delay constraints;
identifying a first library cell whose input capacitance value is closest to the optimal input capacitance value, wherein the first library cell is selected from a technology library;
and
determining a second library cell in the technology library that has a smaller area than the first library cell, and that does not create new timing violations or worsen existing timing violations.

1 more element

Dependencies are inferred from the claim text.

Discretizing gate sizes during numerical synthesis

Life of this patent

Discretizing gate sizes during numerical synthesis

Life of this patent

Abstract

Claims16