Method and system for reproducing prototyping failures in emulation
AssigneeSynopsys, Inc.
InventorsHelena Krupnova, Yogesh Goel
Life of this patent
Estimating the term…
Abstract
A method for simulating a circuit includes running a first prototype of the circuit a predetermined number of cycles behind a second prototype of the circuit, and running a hardware emulator of the circuit in accordance with an input trace received by the first prototype and the second prototype.
Claims42
A method for simulating a circuit, the method comprising:
- running a first prototype of the circuit a predetermined number of cycles behind a second prototype of the circuit;
- and
- running a hardware emulator of the circuit in accordance with an input trace received by the first prototype and the second prototype.
A circuit verification hardware comprising:
- a first prototype of the circuit configured to run a predetermined number of cycles behind a second prototype of the circuit;
- and
- a hardware emulator of the circuit configured to run in accordance with an input trace received by the first prototype and the second prototype.
A system for simulating a circuit configured to:
- run a first prototype of the circuit a predetermined number of cycles behind a second prototype of the circuit;
- and
- run a hardware emulator of the circuit in accordance with an input trace received by the first prototype and the second prototype.
The system of claim 32, wherein the compiler is further configured to program a plurality of logic structures in a field programmable gate array (FPGA) chip.
The system of claim 32, wherein the compiler is further configured to compile a register transfer logic (RTL) inference representing the circuit into a plurality of design objects thereby forming a location database associated with the plurality of design objects, the design objects being implemented respectively in the first prototype, the second prototype, and the hardware emulator.
Dependencies are inferred from the claim text.