Structure, method and system for complementary strain fill for integrated circuit chips

A computer system comprising a processor, an address/data bus coupled to said processor, and computer-readable memory device coupled to communicate with said processor, said memory device containing instructions that when executed by the processor implement a method for complementary strain fill for integrated circuit chips, said method comprising the computer implemented steps of, comprising:

• generating an integrated circuit chip design for an integrated circuit chip;
• generating a tensile layer etch mask design and a compressive layer etch mask design from said integrated circuit chip design;
• identifying active regions of an integrated circuit having a multiplicity of n-channel and a multiplicity of p-channel field effect transistors (FETs);
• identifying low FET density regions of said integrated circuit design, said low FET density regions containing less than 10% FETs by area;
• placing fill shapes in said tensile and compressive layer etch mask designs, said fill shapes placed only in regions of said tensile and compressive layer etch mask designs corresponding to said low FET density regions;
• and
• storing said tensile and compressive etch mask designs on a computer readable device.