Method for Electron Beam Proximity Correction with Improved Critical Dimension Accuracy

A method for making an integrated circuit (IC) using a tape-out system, comprising:

• receiving an IC pattern having a plurality of features;
• fracturing the features into a plurality of polygons wherein each of the polygons has a respective exposure dose during an electron-beam lithography exposure process to image the IC pattern to an electron-sensitive resist layer;
• assigning edge target points to the polygons;
• calculating corrected exposure doses by simulation, each of the corrected exposure doses is associated with only one of the edge target points, by a polygon dose correction module of the tape-out system;
• determining polygon exposure doses based on the corrected exposure doses, wherein each of the polygon exposure doses is associated with one of the polygons;
• and
• preparing a tape-out data of the IC pattern for lithography patterning, wherein the tape-out data includes the plurality of polygons and the polygon exposure doses in pairs.

A method, comprising:

• coating an electron-sensitive resist layer on a substrate;
• and
• performing an electron-beam lithography exposure process to the electron-sensitive resist layer according to an integrated circuit (IC) pattern having a plurality of polygons, wherein the electron-beam lithography exposure process uses respective exposure doses to the polygons, and the plurality of polygons are generated by a procedure that includes
• receiving an IC design layer having a plurality of features;
• fracturing the features into a plurality of polygons;
• assigning edge target points to the polygons;
• calculating corrected exposure doses by simulation, wherein each of the corrected exposure doses is associated with only one of the edge target points;
• and
• determining polygon exposure doses based on the corrected exposure doses, wherein each of the polygon exposure doses is associated with one of the polygons.