Circuit arrangement and method with modified error syndrome for error detection of permanent errors in memories

A circuit arrangement for testing and detecting memory errors in a memory using arbitrary useful data stored in memory, comprising the memory and an error detection circuit,

• wherein the circuit arrangement is designed to write a code word of an error detection code to a memory location of the memory and to store it, wherein the circuit arrangement is furthermore designed to read out a data word stored in the memory at a memory location, and wherein the circuit arrangement is furthermore designed to invert a non-empty subset of bits of a data word which was read out from the memory and to write the read-out data word whose non-empty subset of bits were inverted to the memory location at which the read-out data word was stored,
• wherein the error detection circuit is designed to indicate an error depending on a value of a control signal,
• wherein the error detection circuit is designed, if the control signal assumes a first value, to indicate a memory error if the data word read out from the memory is not a code word of the error detection code,
• wherein the error detection circuit is designed, if the control signal assumes a second value, to indicate a memory error if the data word that is read out from the memory and is inverted in the subset of bits is not a code word of the error detection code,
• wherein the control signal assumes the first value if a code word was written to the memory location of the memory from which the data word was read out,
• wherein the control signal assumes the second value if the data word that is inverted in the subset M of bits and read out from the memory was written to the memory location from which the data word is read out and if a code word of the error detection code, said code word being inverted in the subset M of bits, is not a code word of the error detection code, wherein the first value of the control signal is different from the second value of the control signal, and
• wherein the subset M is a proper subset of all the bits of a data word if a code word that is inverted in the subset M of bits is a code word of the error detection code.

A circuit arrangement, wherein the circuit arrangement comprises:

• a memory;
• an error detection circuit;
• n data input lines;
• and
• n data output lines,
• wherein the circuit arrangement is designed to read out from the memory location of the memory the data word vi=v1i, . . . , vni, which has n digits, onto the n data output lines, wherein in the memory location of the memory, before said data word is read out, the code word vi-1=v1i-1, . . . , vni-1 of the error detection code, said code word being present on the n data input lines, was written to said memory location, or wherein a word vMi-1 having n digits was written to the memory location of the memory, wherein the word vMi-1 is formed by inversion of the bits of a non-empty subset M of bits from a code word vi-1 of the code, wherein, after the word vi-1 or the word vMi-1 was written to a memory location in the memory, no further data word was written to said memory location in the memory until the data word vi was read from said memory location from the memory,
• wherein the code has a code distance d, d≧2, and i≧2 and n≧4,
• wherein the error detection circuit is designed, depending on the value of the control signal if an n-digit code word vi-1 of the code was written to the memory before the n-digit data word vi is read out, to indicate an error if the data word vi read out is not a code word of the code;
• and
• wherein the error detection circuit is designed, if the word vMi-1 having n digits was written to the memory before the n-digit data word vi is read out, if vMi-1 is a code word of the code and if the subset M does not comprise all n bits, to indicate an error if the word vi read out from the memory is not a code word of the code,
• wherein the error detection circuit is designed, if the word vMi-1 having n digits was written to the memory before the n-digit data word vi is read out, if vMi-1 is not a code word of the code, to indicate an error if the word vMi-1 formed from the word vi read out from the memory, said word vMi-1 being formed from vi by inversion of the bits belonging to the subset M, is not a code word of the code,
• wherein the control signal mod assumes the first value if a code word vi-1 of the code was input before the data word is read out, or if a word vMi-1 formed by inversion of the bits belonging to the subset M from a code word of the code was input into the memory before the data word is read out, and if the word vMi-1 is a code word of the code, in which case vMi-1 is a code word of the code and the subset M is a proper subset of all the bits,
• and wherein the control signal mod assumes the second value, which is different from the first value, if a word vMi-1 formed by inversion of the bits belonging to the subset M from a code word of the code was input into the memory before the data word vi is read out, and the word vMi-1 is not a code word of the code.

A circuit arrangement for detecting memory errors, comprising:

• a memory;
• and
• an error detection circuit,
• wherein the error detection circuit is designed for determining errors in the memory,
• wherein the memory is designed to the effect that in the memory useful data bits u=u1, . . . , uk are stored as a code word v=v1, . . . , vn of a code having the length n with k information bits with the code distance d≧2, wherein there are q subsets M1={v1,1, . . . , v1,n1}, . . . , Mq={vq,1, . . . , vq,nq} where q≧1 and ni≦n for i=1, . . . , q of the set M={v1, . . . , vn} of the n components of the code word v=v1, . . . , vn, and at least one of the values n1, . . . , nq is less than n, wherein M1∪M2∪ . . . , ∪Mk=M holds true and such that if v=v1, . . . , vn is a code word of the code, for i=1, . . . , q it is also the case that vMi=v1i, . . . , vni is a code word of the code, wherein vMi is formed from v such that the components of v which are an element of Mi are inverted and the components of v which are not an element of Mi are not inverted, and
• wherein the device is designed to store, in a first step, a code word v1=v11, . . . , vn1 of the code at an address a in the memory,
• wherein the device is furthermore designed to read out, in a second step, a word v2=v12, . . . , vn2, stored at the address a in the memory, wherein the device is designed to carry out the second step after the first step, and wherein, between the first step and the second step, no further word is written to the memory at the address a,
• wherein the error detection circuit is designed to check, in a third step, whether v2 is a code word of the code and, if v2 is not a code word of the code, to indicate an error and to end the processing and, if v2 is a code word of the code, to indicate no error and to continue the processing,
• wherein the device is furthermore designed to store, in a fourth step, a code word v3=(v2)M1 at the address a in the memory, wherein v3=(v2)M1 is determined from v2 such that the components vi2 where i∈{1, . . . , n} of v2 which belong to M1 are inverted and all the components which do not belong to M1 are not inverted, if it has been established in the third step that v2 is a code word of the code,
• wherein the device is furthermore designed to read out, in a fifth step, a word v4 stored at the address a, wherein the device is designed to carry out the fifth step after the fourth step, and wherein, between the fourth step and the fifth step, no further word is written to the memory at the address a, and
• wherein the error detection circuit is furthermore designed to check, in a sixth step, whether v4 is a code word of the code and, if v4 is not a code word of the code, to indicate an error and to end the method and, if v4 is a code word of the code, to indicate no error.

A circuit arrangement for detecting memory errors, comprising:

• a memory;
• and
• an error detection circuit,
• wherein the error detection circuit is designed for determining errors in the memory,
• wherein the memory is designed to the effect that in the memory useful data bits u=u1, . . . , uk are stored as a code word v=v1, . . . , vn of a code having the length n with k information bits with the code distance d≧2, wherein there are q subsets M1={v1,1, . . . , v1,n1}, . . . , Mq={vq,1, . . . , vq,nq} where q≧1 and ni≦n for i=1, . . . , q of the set M={v1, . . . , vn} of the n components of the code word v=v1, . . . , vn, and at least one of the values n1, . . . , nq is less than n, wherein M1∪M2∪ . . . , ∪Mk=M holds true and such that if v=v1, . . . , vn is a code word of the code, for i=1, . . . , q it is also the case that vMi=v1i, . . . , vni is a code word of the code, wherein vMi is formed from v such that the components of v which are an element of Mi are inverted and the components of v which are not an element of Mi are not inverted, and
• wherein the device is designed to store, in a first step, a code word v1=v11, . . . , vn1 of the code at an address a in the memory,
• wherein the device is furthermore designed to read out, in a second step, a word v2=v12, . . . , vn2, stored at the address a in the memory, wherein the device is designed to carry out the second step after the first step, and wherein, between the first step and the second step, no further word is written to the memory at the address a,
• wherein the error detection circuit is designed to check, in a third step, whether v2 is a code word of the code and, if v2 is not a code word of the code, to indicate an error and, if v2 is a code word of the code, to indicate no error,
• wherein the device is furthermore designed to store, in a fourth step, which is carried out after the third step, a code word v3=(v2)2)M1 at the address a in the memory, wherein v3=(v2)M1 is determined from v2 such that the components vi2 where i∈{1, . . . , n} of v2 which belong to M1 are inverted and all the components which do not belong to M1 are not inverted,
• wherein the device is furthermore designed to read out, in a fifth step, a word v4 stored at the address a, wherein the device is designed to carry out the fifth step after the fourth step, and wherein, between the fourth step and the fifth step, no further word is written to the memory at the address a, and
• wherein the error detection circuit is furthermore designed to check, in a sixth step, whether v4 is a code word of the code and, if v4 is not a code word of the code, to indicate an error and, if v4 is a code word of the code, to indicate no error.

A method for detecting memory errors, comprising:

• storing a code word of an error detection code or a code word that is inverted in a subset of bits in the memory at a memory location,
• reading out a data word from the memory from the memory location,
• indicating a memory error if the data word is not a code word of the error detection code, if a control signal assumes a first value, and
• for the case where the control signal assumes a second value, which is different from the first value, and the code word that is inverted in the subset of bits was written to the memory location, determining on the basis of the data word read out from the memory whether a memory error is present if the code word that is inverted in the subset of bits is not a code word of the error detection code.

A method for determining errors in a memory, in which useful data bits u=u1, . . . , uk are stored as a code word v=v1, . . . , vn of a code having the length n with k information bits with the code distance d≧2, wherein there are q subsets M1={v1,1, . . . , v1,n1}, . . . , Mq={vq,1, . . . , vq,nq} where q≧1 and ni≦n for i=1, . . . , q of the set M={v1, . . . , vn} of the n components of the code word v=v1, . . . , vn, wherein M1∪M2∪ . . . , ∪Mk=M holds true and such that if v=v1, . . . , vn is a code word of the code, for i=1, . . . , q it is also the case that vMi=v1i, . . . , vni is a code word of the code, and at least one of the values n1, . . . , nq is less than n wherein vMi is formed from v such that the components of v which are an element of Mi are inverted and the components of v which are not an element of Mi are not inverted, wherein the method comprises:

• in a first step, storing a code word v1=v11, . . . , vn1 of the code at an address a in the memory,
• in a second step, reading out a word v2=v12, . . . , vn2 stored at the address a in the memory, wherein this second step is carried out after the first step, and wherein, between the first step and the second step, no further word was written to the memory at the address a,
• in a third step, checking whether v2 is a code word of the code, wherein, if v2 is not a code word of the code, an error is indicated and the method is ended, and wherein, if v2 is a code word of the code, no error is indicated and the method is continued,
• in a fourth step, storing a code word v3=(v2)M1 at the address a in the memory, wherein v3=(v2)M1 is determined from v2 such that the components vi2 where i∈{1, . . . , n} of v2 which belong to M1 are inverted and all the components which do not belong to M1 are not inverted, if it has been established in the third step that v2 is a code word of the code,
• in a fifth step, reading out a word v4 stored at the address a, wherein the fifth step is carried out after the fourth step and, between the fourth step and the fifth step, no further word is written to the memory at the address a, and
• in a sixth step, checking whether v4 is a code word of the code, wherein, if v4 is not a code word of the code, an error is indicated and the method is ended, and wherein, if v4 is a code word of the code, no error is indicated.

A method for determining errors in a memory, in which useful data bits u=u1, . . . , uk are stored as a code word v=v1, . . . , vn of a code having the length n with k information bits and with the code distance d≧2, wherein there are q subsets useful data bits u=u1, . . . , uk are stored as a code word v=v1, . . . , vn of a code having the length n with k information bits with the code distance d≧2, wherein there are q subsets M1={v1,1, . . . , v1,n1}, . . . , Mq={vq,1, . . . , vq,nq} where q≧1 and ni≦n for i=1, . . . , q of the set M={v1, . . . , vn} of the n components of the code word v=v1, . . . , vn, wherein M1∪M2∪ . . . , ∪Mk=M holds true and such that if v=v1, . . . , vn is a code word of the code, for i=1, . . . , q it is also the case that vMi=v1i, . . . , vni is a code word of the code and at least one of the values n1, . . . , nq is less than n, wherein vMi is formed from v such that the components of v which are an element of Mi are inverted and the components of v which are not an element of Mi are not inverted, wherein the method comprises:

• in a first step, storing a code word v1=v11, . . . , vn1 of the code at an address a in the memory,
• in a second step, reading out a word v2=v12, . . . , vn2 stored at the address a in the memory, wherein this second step is carried out after the first step, and wherein, between the first step and the second step, no further word was written to the memory at the address a,
• in a third step, checking whether v2 is a code word of the code, wherein, if v2 is not a code word of the code, an error is indicated, and wherein, if v2 is a code word of the code, no error is indicated,
• in a fourth step, storing a code word v3=(v2)M1 at the address a in the memory, wherein v3=(v2)M1 is determined from v2 such that the components vi2 where i∈{1, . . . , n} of v2 which belong to M1 are inverted and all the components which do not belong to M1 are not inverted,
• in a fifth step, reading out a word v4 stored at the address a, wherein the fifth step is carried out after the fourth step and, between the fourth step and the fifth step, no further word is written to the memory at the address a, and
• in a sixth step, checking whether v4 is a code word of the code, wherein, if v4 is not a code word of the code, an error is indicated, and wherein, if v4 is a code word of the code, no error is indicated.