Microprocessor accelerated code optimizer
AssigneeSoft Machines, Inc.
InventorMohammad Abdallah
Life of this patent
Estimating the term…
Abstract
A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The optimized microinstruction sequence is output to a microprocessor pipeline for execution. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.
Claims26
In a microprocessor, a method for accelerating code optimization, comprising:
- fetching an incoming microinstruction sequence using an instruction fetch component;
- transferring the fetched macro instructions to a decoding component for decoding into microinstructions;
- performing optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups;
- outputting the optimized microinstruction sequence to a microprocessor pipeline for execution;
- and
- storing a copy of the optimized microinstruction sequence into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.
A microprocessor, comprising:
- an instruction fetch component for fetching an incoming microinstruction sequence;
- a decoding component coupled to the instruction fetch component to receive the fetched macro instruction sequence and decode into a microinstruction sequence;
- an allocation and issue stage coupled to the decoding component to receive the microinstruction sequence perform optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups;
- a microprocessor pipeline coupled to the allocation and issue stage to receive and execute the optimized microinstruction sequence;
- and
- a sequence cache coupled to the allocation and issue stage to receive and store a copy of the optimized microinstruction sequence for subsequent use upon a subsequent hit on the optimized microinstruction sequence.
In a microprocessor, a method for accelerating code optimization, comprising:
- accessing an input microinstruction sequence by using a software-based optimizer instantiated in memory;
- using SIMD instructions to populate a dependency matrix with dependency information extracted from the input microinstruction sequence;
- scanning a plurality of rows of the dependency matrix to perform optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups;
- outputting the optimized microinstruction sequence to a microprocessor pipeline for execution;
- and
- storing a copy of the optimized microinstruction sequence into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.
A microprocessor, comprising:
- an instruction fetch component for fetching an incoming microinstruction sequence;
- a decoding component coupled to the instruction fetch component to receive the fetched macro instruction sequence and decode into a microinstruction sequence;
- an allocation and issue stage coupled to the decoding component to receive the microinstruction sequence perform optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups;
- a microprocessor pipeline coupled to the allocation and issue stage to receive and execute the optimized microinstruction sequence;
- a sequence cache coupled to the allocation and issue stage to receive and store a copy of the optimized microinstruction sequence for subsequent use upon a subsequent hit on the optimized microinstruction sequence;
- and
- a hardware component for moving instructions in the incoming microinstruction sequence.
Dependencies are inferred from the claim text.