Management of caches
AssigneeAdvanced Micro Devices, Inc.
InventorsKai K. Chang, Yasuko Eckert, Gabriel H. Loh, Lisa R. Hsu
Life of this patent
Estimating the term…
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AssigneeAdvanced Micro Devices, Inc.
InventorsKai K. Chang, Yasuko Eckert, Gabriel H. Loh, Lisa R. Hsu
Estimating the term…
A system and method for efficiently powering down banks in a cache memory for reducing power consumption. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, each comprising multiple cache sets. In response to a request to power down a first bank of the multiple banks in the cache array, the cache controller selects a cache line of a given type in the first bank and determines whether a respective locality of reference for the selected cache line exceeds a threshold. If the threshold is exceeded, then the selected cache line is migrated to a second bank in the cache array. If the threshold is not exceeded, then the selected cache line is written back to lower-level memory.
A computing system comprising:
A method executable by at least one processor in a computing system, the method comprising:
A cache controller comprising:
Dependencies are inferred from the claim text.