Methods of making multi-state non-volatile memory cells

A method of making a semiconductor device, comprising:

• depositing a first charge storage layer on a top surface of an active region in a substrate;
• depositing a first layer comprising one of a group consisting of metal and polysilicon on the active region;
• etching the first layer to leave a first line and a second line of the first layer across the active region;
• after etching the first layer, depositing a second charge storage layer over the active region;
• depositing a second layer comprising one of a group consisting of metal and polysilicon over the second charge storage layer;
• removing portions of the second layer and the second charge storage layer to leave a third line between the first line and the second line and separated from the first line and the second line by a remaining portion of the second charge storage layer;
• forming a first spacer on a first side of the first line, wherein the first side of the first line is away from the third line;
• forming a second spacer on a first side of the second line, wherein the first side of the second line is away from the third line;
• forming a drain region in the substrate, wherein the drain region includes a drain region extension under the first spacer;
• and
• forming a source region in the substrate, wherein the source region includes a source region extension under the second spacer.

A method of making a semiconductor device, comprising:

• forming a first charge storage layer on a top surface of a semiconductor substrate;
• forming first and second outer conductive lines on portions of the first charge storage layer;
• forming a second charge storage layer on the top surface, the second charge storage layer having a first side adjoining a first sidewall of the first outer conductive line;
• forming a third charge storage layer on the top surface, the third charge storage layer having a first side adjoining a first sidewall of the second outer conductive line;
• forming a first spacer on a second sidewall of the first outer conductive line, wherein the second sidewall of the first outer conductive line is away from the second outer conductive line;
• forming a second spacer on a second sidewall of the second outer conductive line, wherein the second sidewall of the second outer conductive line is away from the first outer conductive line;
• forming a source region in the substrate on a first side of the first outer conductive line, wherein the source region includes a source region extension under the first spacer;
• and
• forming a drain region in the substrate on a first side of the second outer conductive line, wherein the drain region includes a drain region extension under the second spacer.