Clustering for processing of circuit design data
AssigneeMentor Graphics Corporation
InventorManjit Borah
Life of this patent
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Abstract
Nodes in microdevice design data are selected to form initial clusters. Typically the nodes are selected based upon the type of process to be performed on the design data. The initial clusters are then be grown, merged with other nodes, or come combination of both until the processing costs of the final clusters are compatible with the amount of resources that will be used to process the design data.
Claims23
A method of partitioning portions of a circuit design for an electronic design automation process, comprising:
- generating one or more initial clusters of nodes from the circuit design by employing a computing system
- identify one or more critical paths in the circuit design that do not meet specified timing requirements,
- select one or more nodes in the critical paths that have timing violations, and
- grow the initial clusters of nodes from the selected nodes, wherein each initial cluster of nodes includes at least one node having a timing violation exceeding a threshold value and having a logical connection to at least another node in the initial cluster of nodes;
- employing a computing system to create one or more final clusters of nodes from the initial clusters of nodes based upon processing weight values for processing the final clusters of nodes according to the electronic design automation process;
- and
- employing a computing system to partition the circuit design according to the final clusters of nodes.
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An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
- identifying one or more critical paths in a circuit design that do not meet specified timing requirements;
- selecting one or more nodes in the critical paths based on timing delays associated with the one or more nodes;
- forming one or more initial clusters of nodes by grouping the selected nodes with one or more additional nodes in the circuit design based on timing delays associated with the one or more additional nodes, wherein each additional node grouped into a corresponding initial cluster of nodes has a logical connection to at least another node in the corresponding initial cluster of nodes;
- generating one or more final clusters of nodes based, at least in part, on the initial clusters of nodes and processing weight values for processing the final clusters of nodes according to the electronic design automation process;
- and
- partitioning the circuit design according to the final clusters of nodes.
Dependencies are inferred from the claim text.