Method and Apparatus for Multi-chip Reduced Pin Cross Triggering To Enhance Debug Experience

A first integrated circuit, comprising:

• a plurality of trigger sources and trigger sinks;
• a cross trigger interconnect structure configured to interconnect the plurality of trigger sources and trigger sinks;
• a time-division packetizing transmitter (TDPTx) circuit coupled to the cross trigger interconnect structure and to a data output pin and configured to connect to a second integrated circuit;
• and a
• a time-division packetizing receiver (TDPRx) circuit coupled to the cross trigger interconnect structure and to a data input pin and configured to connect to a third integrated circuit,
• wherein the TDPRx circuit is configured to perform operations comprising:
• receiving a time-division packetizing (TDP) signal from the third integrated circuit, the TDP signal having a sequence start signature and a number of slots, wherein each slot includes a count value configured to indicate whether the slot is free or contains a trigger value;
• determining whether each slot in the TDP signal contains a first trigger value based on a first count value of the slot;
• and
• passing the first trigger value in each slot containing the first trigger value to the cross trigger interconnect structure and modifying that slot's first count value;
• wherein the TDPTx circuit is configured to perform operations comprising:
• retransmitting to the second integrated circuit the TDP signal including the sequence start signature and the number of slots in which each slot includes one of:
• the first trigger value when that slot's modified first count value indicates that slot contains the first trigger value;
• a second trigger value obtained from the cross trigger interconnect structure along with a second count value indicating the slot contains the second trigger value when the first integrated circuit has the second trigger value to transmit and that slot's modified first count value indicates the slot is free;
• and
• an empty slot with the second count value indicating that slot is free when the first integrated circuit does not have the second trigger value to transmit and that slot's modified first count value indicates that the slot is free.

A non-transitory processor-readable medium having stored thereon processor-executable software instructions configured to be executed by an interconnected hardware core to perform operations comprising:

• initiating, by a first interconnected hardware core, a time-division packetizing (TDP) signal having a sequence start signature and a number of slots, wherein each slot includes a count value configured to indicate whether the slot is free or contains a trigger value;
• sending, by the first interconnected hardware core, the TDP signal to a second interconnected hardware core;
• receiving, by the first interconnected hardware core, the TDP signal by a third interconnected hardware core;
• determining, by the first interconnected hardware core, whether each slot contains a first trigger value based on a first count value of the slot;
• for each slot containing the first trigger value, passing the first trigger value to a cross trigger interconnect structure of the first interconnected hardware core and modifying that slot's first count value;
• retransmitting the TDP signal including the sequence start signature and the number of slots in which each slot includes one of:
• the first trigger value when that slot's modified first count value indicates that slot contains the first trigger value;
• a second trigger value obtained from the cross trigger interconnect structure along with a second count value indicating the slot contains the second trigger value when the first interconnected hardware core has the second trigger value to transmit and that slot's modified first count value indicates the slot is free;
• and
• an empty slot with the second count value indicating that slot is free when the first interconnected hardware core does not have the second trigger value to transmit and that slot's modified first count value indicates that the slot is free.

A circuit for use in debugging a plurality of interconnected hardware cores, comprising:

• means for initiating within a first interconnected hardware core a time-division packetizing (TDP) signal having a sequence start signature and a number of slots, wherein each slot includes a count value configured to indicate whether the slot is free or contains a trigger value;
• means for sending the TDP signal to a second interconnected hardware core;
• means for receiving the TDP signal by a third interconnected hardware core;
• means for determining whether each slot contains a first trigger value based on a first count value of the slot;
• means for passing the first trigger value to a cross trigger interconnect structure of the first interconnected hardware core and means for modifying that slot's first count value for each slot containing the first trigger value;
• means for retransmitting the TDP signal including the sequence start signature and the number of slots in which each slot includes one of:
• the first trigger value when that slot's modified first count value indicates that slot contains the first trigger value;
• a second trigger value obtained from the cross trigger interconnect structure along with a second count value indicating the slot contains the second trigger value when the first interconnected hardware core has the second trigger value to transmit and that slot's modified first count value indicates the slot is free;
• and
• an empty slot with the second count value indicating that slot is free when the first interconnected hardware core does not have the second trigger value to transmit and that slot's modified first count value indicates that the slot is free.