Cache debug system for programmable circuits

A method of debugging an integrated circuit having programmable circuitry and system-on-chip circuitry, comprising:

• programming the programmable circuitry to implement a debug master in the programmable circuitry;
• issuing a command with the debug master;
• providing the command from the debug master to a command translator over system-on-chip interconnects in the system-on-chip circuitry;
• with the command translator, translating the command;
• and
• with a memory coherency control unit in a microprocessor unit subsystem in the system-on-chip circuitry, processing the translated command from the command translator.

A method of debugging an integrated circuit that contains programmable circuitry and a microprocessor unit subsystem, comprising:

• programming the programmable circuitry to form a debug master;
• with an external debug tool, receiving instructions on debug operations to be performed from a user;
• in response to the instructions, directing the debug master to issue a command on interconnects in the integrated circuit;
• with a command translator, translating the command issued by the debug master;
• and
• with a memory coherency control unit in the microprocessor unit subsystem, receiving the translated command.