Apparatus and method for controlling controllable clock source to generate clock signal with frequency transition
AssigneeMediatek Inc.
InventorsYou-Ming Tsao, Chun-Liang Chen, Chen-Chia Lee
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Abstract
A clock generator includes a controllable clock source and a frequency hopping controller. The controllable clock source generates a clock signal to a clock-driven device. The frequency hopping controller controls the controllable clock source to make the clock signal have at least one frequency transition from one clock frequency to another clock frequency, wherein the controllable clock source stays in a frequency-locked state during a time period of the at least one frequency transition.
Claims20
A clock generator, comprising:
- a controllable clock source, configured to generate a clock signal to a clock-driven device;
- and
- a frequency hopping controller, configured to control the controllable clock source to make the clock signal have at least one frequency transition from one clock frequency to another clock frequency, wherein the controllable clock source stays in a frequency-locked state during a time period of the at least one frequency transition.
A clock generating method, comprising:
- utilizing a controllable clock source to generate a clock signal to a clock-driven device;
- and
- controlling the controllable clock source to make the clock signal have at least one frequency transition from one clock frequency to another clock frequency, wherein the at least one frequency transition is controlled to prevent the controllable clock source from leaving a frequency-locked state during a time period of the at least one frequency transition.
An electronic device, comprising:
- a memory controller, configured to control access of a memory device;
- and
- a processor, configured to perform a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.
An electronic device, comprising:
- a processor, configured to perform a calibration operation to find a skew value between a data strobe (DQS) signal and a clock signal of a memory device;
- and
- a clock generator, comprising:
- a controllable clock source, configured to generate the clock signal to the memory device;
- and
- a frequency hopping controller, configured to control frequency hopping of the controllable clock source according to the skew value.
Dependencies are inferred from the claim text.