Harmonic Detector of Critical Path Monitors

A method for monitoring a reference clock signal of a computing system, comprising:

• generating a derived clock signal with a frequency one-half of the reference clock signal;
• generating a first delayed clock signal dependent upon the derived clock signal, wherein the first delayed clock signal is delayed from the derived clock signal by a period corresponding to an expected maximum frequency of the reference clock signal;
• generating a second delayed clock signal dependent upon the derived clock signal, wherein the second delayed clock signal is delayed from the derived clock signal by an amount of time greater than the period of an even harmonic of the expected maximum frequency and less than one-half of the period of the next larger odd harmonic of the expected maximum frequency;
• sampling the plurality of delayed clock signals to generate a respective plurality of clock samples;
• comparing each clock sample of the plurality of clock samples to the derived clock signal;
• determining, dependent upon the comparisons, if the actual frequency of the reference clock signal is greater than the expected maximum frequency;
• and
• generating an alert signal if the actual frequency is greater than the expected maximum frequency.

An apparatus, comprising:

• a reference clock circuit configured to generate a reference clock signal, wherein the reference clock signal has an expected minimum period;
• a frequency divider circuit coupled to the reference clock circuit, wherein the frequency divider is configured to generate a derived clock signal, wherein a period of the derived clock signal is greater than a period of the reference clock signal;
• a delay unit coupled to the frequency divider, wherein the delay logic block is configured to:
• generate a first delayed clock signal from the derived clock signal, wherein the first delayed clock signal is delayed by the expected minimum period of the reference clock;
• generate a second delayed clock signal from the derived clock signal, wherein the second delayed clock signal is delayed by an amount of time greater than an even harmonic of a frequency whose period is the expected minimum period and less than one-half of the next larger odd harmonic of the frequency whose period is the expected minimum period;
• a sampling unit coupled to the delay logic block and coupled to the reference clock circuit, wherein the sampling unit is configured to sample and store, for one reference clock period, the first delayed clock signal and the second delayed clock signal and output each of the stored sample signals;
• and
• a comparison unit coupled to the sampling unit, wherein the comparison unit is configured to:
• receive the stored sample signals and the derived clock signal;
• compare the stored sample signals to the derived clock signal;
• determine if the actual period of the reference clock signal is less than the expected minimum period;
• and
• assert an alert signal responsive to a determination the period of the reference clock signal is less than the expected minimum period.