Techniques for Managing Power and Performance of Multi-Socket Processors

At least one machine readable medium comprising a plurality of instructions that in response to being executed on a system cause the system to:

• monitor activity of a first processor circuitry in a first processor socket to determine a utilization rate of the first processor circuitry, the first processor circuitry coupled to a second processor in a second processor socket via one or more communication links capable of providing access to a cache for the first processor circuitry;
• and
• cause a first power state of the first processor circuitry to be changed to a higher power state based on the utilization rate.

A method comprising:

• monitoring activity of a first processor circuitry in a first processor socket to determine a utilization rate of the first processor circuitry, the first processor circuitry coupled to a second processor in a second processor socket via one or more communication links capable of providing access to a cache for the first processor circuitry;
• and
• changing a first power state of the first processor circuitry based on the utilization rate.