Restricting Clock Signal Delivery Based On Activity In A Processor
AssigneeIntel Corporation
InventorsAlexander Gendler, George Leifman
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Abstract
In an embodiment, a processor has a core to execute instructions which includes a first cache memory, a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, and a core activity monitor logic to monitor activity of the core and, responsive to a miss in the first cache memory, to send a first restriction command to cause the clock generation logic to reduce delivery of the first clock signal to at least one of the units to a first frequency less than a frequency of the first clock signal. Other embodiments are described and claimed.
Claims20
A processor comprising:
- a core to execute instructions, the core including a first cache memory, a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, and a core activity monitor logic to monitor activity of the core and, responsive to a miss in the first cache memory, to send a first restriction command to cause the clock generation logic to reduce delivery of the first clock signal to at least one of the plurality of units to a first frequency less than a frequency of the first clock signal.
A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- receiving information regarding a cache memory miss in a monitor logic of a core of a processor associated with the cache memory;
- sending a clock restriction command, from the monitor logic to a clock generation circuit of the core, with a restriction level responsive to the information;
- and
- controlling the clock generation circuit according to the restriction level to drive a restricted clock signal to at least one functional unit of the core, wherein the restricted clock signal includes a reduced number of cycles of a clock signal of the core.
A system comprising:
- a multicore processor including a plurality of cores, each core including at least one cache memory, a clock generator to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a clock restriction command and to cause reduced delivery of the first clock signal to at least one of the plurality of units without execution of a frequency change protocol and an activity monitor to communicate the clock restriction command to the restriction logic responsive to an event occurring in the core, a power controller coupled to the plurality of cores, and a clock logic to provide the first clock signal to at least one of the plurality of cores;
- and
- a dynamic random access memory (DRAM) coupled to the multicore processor.
Dependencies are inferred from the claim text.