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US 2015/0033050 A1Published application
Semiconductor integrated circuit and computing device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsAmjad QADAN, Neil PANCHAL
Life of this patent
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Abstract
A semiconductor integrated circuit and a computing system including the same are provided. The semiconductor integrated circuit includes: an integrated clock gating cell including a clock output node; and clock-based cells each including a clock input node. The clock output node of the integrated clock gating cell and the clock input nodes of the clock-based cells are aligned on a straight line and commonly connected to a clock gating path.
Claims20
A semiconductor integrated circuit comprising:
- a first integrated clock gating cell comprising a first clock output node;
- and
- first clock-based cells each comprising a first clock input node,
- wherein the first clock output node of the first integrated clock gating cell and the first clock input nodes of the first clock-based cells are aligned on a straight line and commonly connected to a first clock gating path.
1 more element
A computing system comprising:
- a main memory;
- a storage;
- a processor configured to control the main memory and the storage;
- a modem configured to communicate with a first external entity according to a control of the processor;
- a user interface configured to receive a signal from a second external entity and output a signal to the second external entity according to a control of the processor;
- and
- a clock generating circuit configured to generate a clock signal and transmit the generated clock signal to at least one of the processor and the modem,
- wherein the at least one of the processor and the modem comprises an aligned clock gating tree structure operating in response to the transmitted clock signal,
- wherein the aligned clock gating tree structure comprises an integrated clock gating cell configured to receive the clock signal and output a gated clock signal and a plurality of clock-based cells configured to receive the output gated clock signal from the integrated clock gating cell, and
- wherein the integrated clock gating cell and the plurality of clock-based cells are concentrically arranged such that a length of a longest clock gating path along which the gated clock signal is transmitted to the clock-based cells from the integrated clock gating cell is equal to or less than a reference value.
7 more elements
A semiconductor integrated circuit comprising:
- a first integrated clock gating cell configured to output a gated clock signal along a first clock gating path that is a straight line;
- and
- first clock-based cells each configured to receive the output gated clock signal along the first clock gating path,
- wherein the first integrated clock gating cell and the first clock-based cells are arranged such that a longest transmission length on the first clock gating path along which the gated clock signal is transmitted to the first clock-based cells from the first integrated clock gating cell is equal to or less than a reference value.
1 more element
Dependencies are inferred from the claim text.