US 2015/0033045 A1 · Power Supply Droop Reduction Using Feed Forward Current Control

Abstract

An apparatus for performing instruction throttling for a computing system is disclosed. The apparatus may include a first counter, a second counter, and a control circuit. The second counter may be configured to increment in response to a determination that a processing cycle of a processor has completed. The control circuit may be configured to initialize the first and second counters, detect the processor has issued and instruction, decrement the first counter in response to the detection of the issued instruction, block the processor from issuing instructions dependent upon the a value of the first counter, reset the first counter dependent upon a value of the second counter, and reset the second counter in response to a determination that the value of the second counter is greater than a pre-determined value.

Claims20

Dependent claims

An apparatus, comprising:

a first counter configured to count a number of power credits;
a second counter configured to increment responsive to completion of a processing cycle of a processor;
and
a control circuit coupled to the power credit counter and the cycle counter, wherein the control circuit is configured to:
initialize the first counter;
initialize the second counter;
detect an issue of an instruction in the processor;
decrement the first counter dependent upon the detection of the issue of the instruction;
block the processor from issuing instructions dependent upon a value of the first counter;
reset the power credit counter dependent upon a value of the second;
and
reset the second counter responsive to a determination that the value of the second counter is greater than a pre-determined value.

9 more elements

Dependencies are inferred from the claim text.

Power Supply Droop Reduction Using Feed Forward Current Control

Life of this patent

Power Supply Droop Reduction Using Feed Forward Current Control

Life of this patent

Abstract

Claims20