Methods and Circuits for Dynamically Scaling DRAM Power and Performance
AssigneeRambus Inc.
InventorsEly Tsern, Thomas Vogelsang, Craig Hampel, Scott C. Best
Life of this patent
Estimating the term…
Abstract
A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.
Claims14
(canceled)
A memory controller comprising:
- a register to store a mode setting indicative of a first mode or a second mode;
- an input/output (I/O) interface coupled to the register to receive data at a first data bandwidth in the first mode and a second data bandwidth in the second mode;
- and
- a command architecture to convey a command to an external device to define a variable voltage, the variable voltage used by a memory device to transmit the data to the I/O interface and including a first voltage associated with the first mode and a second voltage associated with the second mode.
A method of controlling speed performance of a memory device, the method comprising:
- issuing a first mode command to the memory device, the first mode command to cause the memory device to enter a high-performance mode;
- communicating first data at a first data bandwidth with the memory device in the high-performance mode;
- issuing a second mode command to the memory device, the second mode command to cause the memory device to enter a low-power mode;
- and
- communicating second data at a second data bandwidth with the memory device in the low-power mode.
Dependencies are inferred from the claim text.