Instruction set architecture with opcode lookup using memory attribute
AssigneeInternational Business Machines Corporation
InventorsAdam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
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Abstract
A method and circuit arrangement decode instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded.
Claims25
A method of executing instructions from an instruction set architecture in a processing unit, the method comprising:
- receiving an instruction from an instruction stream, the instruction including an extended decode mode indicator that indicates whether the instruction is decoded using an extended decode mode;
- accessing a page table entry associated with a page of memory within which the instruction is stored to retrieve a decode-related attribute associated with the page of memory, wherein the decode-related attribute comprises an index;
- accessing a primary opcode table using the index to select a primary opcode associated with the index from among a plurality of primary opcodes in the primary opcode table;
- and
- in response to the extended decode mode indicator indicating that the instruction is decoded using the extended decode mode, decoding the instruction using the instruction and the selected primary opcode from the primary opcode table.
A method of executing instructions from an instruction set architecture in a processing unit, the method comprising:
- in response to receiving an instruction in an instruction stream, accessing a decode-related attribute in a memory address translation data structure, wherein the instruction is associated with an address at which the instruction is stored in an address space, wherein the memory address translation data structure is used to perform memory address translation for instructions in the instruction stream, and wherein the decode-related attribute is accessed using at least a portion of the address;
- and
- decoding at least a portion of an opcode for the instruction using the decode-related attribute.
A circuit arrangement, comprising:
- a processing unit;
- a memory address translation data structure for use in performing memory address translation for instructions in an instruction stream being executed by the processing unit, wherein the memory address translation data structure includes a decode-related attribute associated with an instruction from the instruction stream, wherein the instruction is associated with an address at which the instruction is stored in an address space, and wherein the decode-related attribute is accessed using at least a portion of the address;
- and
- decode logic configured to access the decode-related attribute in the memory address translation data structure and decode at least a portion of an opcode for the instruction using the decode-related attribute.
Dependencies are inferred from the claim text.