Method, apparatus, and system for transactional speculation control instructions

A method comprising:

• decoding an xAcquire instruction including a lock instruction and a lock elision prefix;
• eliding the lock instruction in response to decoding the xAcquire instruction including the lock instruction and the lock elision prefix;
• and
• executing a critical section started by the xAcquire instruction tentatively with memory accesses from the critical section being tracked in response to eliding the lock instruction.

A non-transitory computer readable medium including code, when executed, to cause a machine to perform the operations of:

• decoding an xAcquire instruction including a lock instruction and a lock elision prefix;
• eliding the lock instruction in response to decoding the xAcquire instruction including the lock instruction and the lock elision prefix;
• and
• executing a critical section started by the xAcquire instruction tentatively with memory accesses from the critical section being tracked in response to eliding the lock instruction.

A non-transitory computer readable medium including code, when executed, to cause a machine to perform the operations of:

• determining a critical section in program code demarcated by a lock instruction and a lock release instruction;
• modifying the lock instruction into a lock instruction with a lock elision prefix in response to determining the critical section;
• and
• modifying the lock release instruction into a lock instruction with a lock release elision prefix.

An apparatus comprising:

• decode logic configured to decode a lock release instruction including a lock release elision hint field set to hint that the lock release instruction is to be elided;
• and
• lock elision logic coupled to the decode logic, the lock elision logic being configured to determine if the lock release instruction is to be elided based on the lock release elision hint field being set to hint that the lock release instruction is to be elided and eliding the lock release instruction in response to determining the lock release instruction is to be elided;
• and
• commit logic coupled to the lock elision logic, the commit logic being configured to attempt to commit a critical section ended by the lock release instruction in response to the lock elision logic eliding the lock release instruction.

A method comprising:

• decoding an xRelease instruction including a lock release instruction and a lock release elision prefix;
• eliding the lock release instruction in response to decoding the xRelease instruction including the lock release instruction and the lock release elision prefix;
• and
• attempting to commit a critical section ended by the xRelease instruction in response to decoding the xRelease instruction.

A non-transitory computer readable medium including code, when executed, to cause a machine to perform the operations of:

• decoding an xRelease instruction including a lock release instruction and a lock release elision prefix;
• eliding the lock release instruction in response to decoding the xRelease instruction including the lock release instruction and the lock release elision prefix;
• and
• attempting to commit a critical section ended by the xRelease instruction in response to decoding the xRelease instruction.

An apparatus comprising:

• decode logic configured to decode an xBegin instruction to start a transaction, the xBegin instruction to include a reference to a fall back address;
• a register configured to be updated with the fallback address in response to the decode logic decoding the xBegin instruction
• checkpoint logic configured to checkpoint a set of architecture state registers in response to the decode logic decoding the xBegin instruction;
• and
• tracking logic configured to rack memory accesses from a processing element associated with the xBegin instruction in response to the decode logic decoding the xBegin instruction.

A method comprising:

• decoding a xBegin instruction to start a transaction, the xBegin instruction to include a reference to a fall back address;
• in response to the decode logic decoding the xBegin instruction,
• registering the fallback address;
• checkpointing a set of architecture state registers;
• and
• tracking memory accesses from a processing element associated with the xBegin instruction.

An apparatus comprising:

• decode logic configured to decode an xAbort instruction to abort a speculative region;
• checkpoint logic to restore an architectural register state to a checkpoint in response to the decode logic decoding the xAbort instruction;
• control logic configured to discard tentative memory updates performed during the speculative region in response to the decode logic decoding the xAbort instruction;
• and
• status storage logic configured to store an abort status in response to the decode logic decoding the xAbort instruction.

An apparatus comprising:

• decode logic configured to decode an xTest instruction including a reference to a speculation field;
• status logic configured to determine a speculation status in response to the xTest instruction;
• and
• the speculation field being configured to be updated to a speculation value in response to a processing element associated with the decode logic being in a speculation mode and being updated to a non-speculation value in response to the processing element being in a non-speculation mode.