Execution-aware memory protection
AssigneeIntel Corporation
InventorsPatrick Koeberl, Steffen Schulz
Life of this patent
Estimating the term…
Abstract
Execution-Aware Memory protection technologies are described. A processor includes an instruction fetch unit to fetch instructions of applications executing in a multitasking environment and an execution unit to execute the instructions. A memory protection unit (MPU) enforces memory access control of the applications by defining an instruction region (I-space) and a data region (D-space and linking the I-space to the D-space. When the MPU determining whether an instruction address is within the I-space and whether a data address of a data access operation is within the D-space. The MPU issues a memory protection fault for the data access operation when either the instruction address is not within the I-space or the data address is not within the D-space.
Claims25
A processor comprising:
- an instruction fetch unit to fetch a plurality of instructions for a plurality of applications executing in a multitasking environment;
- an execution unit to execute the plurality of instruction;
- and
- a memory protection unit (MPU) to enforce memory access control for the plurality of applications, wherein the MPU is operable to:
- define an instruction region (I-space) in an I-space register and a data region (D-space) in a D-space register;
- link the I-space to the D-space;
- receive an instruction address for a first instruction of the plurality of instructions from the instruction fetch unit and a data address of a data access operation for the first instruction from the execution unit;
- determine whether the instruction address and data address are within the I-space defined by the I-space register and within the D-space defined the D-space register;
- and
- issue a memory protection fault for the data access operation when the instruction address and data address are not within the I-space and D-space.
A method comprising:
- defining, by a memory protection unit (MPU) of a processor, an instruction region (I-space) in an I-space register and a data region (D-space) in a D-space register;
- linking the I-space to the D-space;
- receiving, by the MPU, an instruction address for a first instruction;
- receiving, by the MPU, a data address of a data access operation for the first instruction;
- determining whether the instruction address is within the defined I-space;
- determining whether the data address is within the defined D-space associated with the defined I-space;
- and
- issuing a memory protection fault for the data access operation when either the instruction address is outside the I-space or the data address is outside the D-space.
A processor comprising:
- a processor core;
- a memory device operable to store code memory and data memory;
- and
- a memory protection unit MPU coupled between the processor core and the memory device, wherein the MPU is configured to:
- define a code region in the code memory and a data region in the data memory;
- link the code region to the data region;
- receive an instruction address, a data address and a transaction type from the processor core;
- and
- issue a memory protection fault when either the instruction address is not within the code region or when the data address is not within the data region.
Dependencies are inferred from the claim text.