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US 2015/0032995 A1Published application
Processors operable to allow flexible instruction alignment
AssigneeAltera Corporation
InventorJames Loran Ball
Life of this patent
Estimating the term…
Abstract
Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.
Claims20
A method comprising:
- performing by a first subcircuitry a multi-byte non-branch instruction;
- and
- performing by the first subcircuitry a multi-byte branch instruction, the branch instruction having a different multi-byte alignment from the non-branch instruction, wherein the multi-byte branch instruction is performed without first performing a multiplication with an immediate field associated with the multi-byte branch instruction,
- wherein the first subcircuitry is used to calculate a target address even if the target address contains a byte aligned instruction or a multi-byte aligned instruction.
1 more element
A processor core comprising:
- a program counter operable to maintain a program counter value;
- and
- a common subcircuitry arranged to:
- perform a multi-byte non-branch instruction, and
- perform a multi-byte branch instruction, the branch instruction having a different multi-byte alignment from the non-branch instruction, wherein the multi-byte branch instruction is performed without first performing a multiplication with an immediate field associated with the multi-byte branch instruction,
- wherein the common subcircuitry is operable to calculate a target address even if the target address contains
- a byte aligned instruction or a multi-byte aligned instruction.
4 more elements
A system comprising:
- a processor having a program counter and a common subcircuitry arranged to:
- perform a multi-byte non-branch instruction, and
- perform a multi-byte branch instruction, the branch instruction having a different multi-byte alignment from the non-branch instruction, wherein the multi-byte branch instruction is performed without first performing a multiplication with an immediate field associated with the multi-byte branch instruction,
- wherein the common subcircuitry is operable to calculate a target address even if the target address contains a byte aligned instruction or a multi-byte aligned instruction.
1 more element
Dependencies are inferred from the claim text.