Method and System for Improving Serial Port Memory Communication Latency and Reliability
AssigneeLattice Semiconductor Corporation
InventorsAlan Ruberg, Seung-Jong Lee, Hyung Rok Lee, Daeyun Shim, Dongyun Lee, Sungjoon Kim, Anu Murthy
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Abstract
A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.
Claims20
A method for communicating between a host computer system and a memory, the method comprising:
- configuring a port binding control register to specify a first bound group of ports from a plurality of ports of the memory;
- and
- during a first memory operation, receiving at the memory, a first plurality of serial data streams communicated from the host computer system to the memory via the first bound group of ports of the memory, the first plurality of serial data streams received in parallel.
A memory comprising:
- a memory core;
- a plurality of configurable ports to communicatively couple the memory core to a host processor;
- a port binding control register configurable to specify a first bound group of ports of the plurality of configurable ports of the memory during a first memory operation,
- wherein during the first memory operation, the first bound group of ports receives a first plurality of serial data streams communicated from the host computer system to the memory.
A method for communicating between a host computer system and a memory, the method comprising:
- configuring a port binding control register to specify a first bound group of ports from a plurality of ports of the memory;
- and
- during a first memory operation, communicating from the host processor to the memory, a first plurality of serial data streams via the first bound group of ports of the memory, the first plurality of serial data streams communicated in parallel.
Dependencies are inferred from the claim text.